Hardware Engineer - Physical Design

Achronix Semiconductor

Posted Sept. 17, 2023

Don't forget to mention FPGAjobs in your application. We are a small team, and these mentions are a huge help to us!

<div class="content-intro"><p>Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.</p></div><h2 id="id-(6200-1031)HardwareEngineer-PhysicalDesign-JobDescription/Responsibilities">Job Description/Responsibilities</h2> <p>The successful candidate will engineer the physical implementation of blocks from RTL to GDS in advanced FinFet technology nodes (7nm/12nm/14nm/16nm) and below, sharing responsibilities across design and verification. Responsibilities include the following:</p> <ul> <li>RTL synthesis, writing timing, area, and other relevant constraints</li> <li>Floorplanning, power grid implementation, clock tree synthesis, place and route</li> <li>Parasitic extraction and physical design verification</li> <li>Static timing analysis, and timing closure</li> <li>Lint, design for test, test coverage</li> <li>EM/IR verification and logic equivalence/formal verification</li> <li>Low-power design and power optimization</li> <li>Collaborate with other members of the team to optimize design in context</li> <li>Work with other team members to improve methodologies and flows</li> <li>Support post-silicon product bring-up and debug, timing and power characterization</li> </ul> <h2 id="id-(6200-1031)HardwareEngineer-PhysicalDesign-RequiredSkills">Required Skills</h2> <ul> <li>Experience with digital VLSI CMOS circuit design and physical design in advanced FinFet technology nodes</li> <li>Experience with HDLs such as Verilog</li> <li>Experience with industry-standard tools such as Design Compiler, ICC2, PrimeTime, Tetramax, RedHawk, ICV, Caliber LVS/DRC</li> <li>Excellent debugging skills</li> <li>Comfortable programming in a scripting language (e.g., Python or Perl) and writing full programs from scratch (e.g. 5000+ lines of code)</li> <li>Familiarity with revision-control systems (e.g., Perforce, git)</li> <li>Familiarity with using and/or designing FPGAs is a plus</li> <li>Well organized, punctual, excellent communication skills; ability to operate without direct supervision; ability to collaborate with other team members</li> </ul> <h2 id="id-(6200-1031)HardwareEngineer-PhysicalDesign-EducationandExperience">Education and Experience</h2> <ul> <li>MS in Electrical Engineering with 3-10 years experience</li> </ul> <p>&nbsp;</p> <p>The compensation range for this position is $145,000 - $200,000. Salary ranges dependent on experience and location.</p>