Staff RTL Design & Architecture Engineer

Achronix Semiconductor

Posted Sept. 13, 2023

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<div class="content-intro"><p>Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.</p></div><h2 id="id-(6500-1013)VerificationEngineer(DDR)-JobDescription/Responsibilities">Job Description/Responsibilities</h2> <p>The successful candidate will lead and contribute to the Architecture, design, verification and silicon validation of high-performance SoCs</p> <h3 id="id-(6500-1029)StaffRTLDesign&amp;ArchitectureEngineer-PrimaryJobResponsibilities">Primary Job Responsibilities</h3> <ul> <li>Responsible for SoC front end architecture and design, defining microarchitecture specifications</li> <li>Perform RTL coding using SystemVerilog and/or Verilog. Perform feasibility study on different third party IP and integrate IP at the SoC level</li> <li>Develop IP. Work closely with verification team and help define test plan, run tests and debug designs</li> <li>Lead the performance model development. Participate in design reviews of hardware systems and related software systems</li> <li>Run Lint, CDC, Synthesis, STA and formal verification tools. Work closely with backend team on floorplan, constraints definition and timing analysis</li> <li>Support FPGA prototyping and post-silicon system bring-up</li> <li>Collaborate with internal and external team members on architectural decisions, development flows and methodologies</li> </ul> <p>&nbsp;</p> <h2 id="id-(6500-1013)VerificationEngineer(DDR)-RequiredSkills">Required Skills</h2> <ul> <li>Expert RTL developer having experience with SystemVerilog, ASIC techniques and design flows, including synthesis and timing closure</li> <li>Excellent communication and documentation skills</li> <li>Experience with one or more of the following technology areas: <ul> <li>High speed I/O and SerDes</li> <li>Ethernet, including high-speed links (100 Gbps+) and priority-based flow control (PFC)</li> <li>NoC design SoC protocols, such as CHI, AXI, ACE, APB, etc.</li> <li>CPU microarchitecture (e.g., x86, ARM, SPARC, MIPS, RISC-V, POWER) and/or coherent caching systems.</li> <li>Inter-device protocols (e.g., PCIe, CXL)</li> </ul> </li> <li>Experience with one or more industry standard (or proprietary) interconnect technologies (e.g., AMBA, CHI, CCIX, CXL, etc.)</li> <li>Post-silicon validation and debug experience</li> <li>FPGA design experience is a plus</li> <li>Knowledge of low-power design, tools and methodologies, including power intent UPF specifications, a plus.</li> </ul> <p>&nbsp;</p> <h2 id="id-(6500-1013)VerificationEngineer(DDR)-EducationandExperience">Education and Experience</h2> <ul> <li>BS with 8+ years of experience or MS with 6+ years of experience or PhD with 3+ years of experience in Electrical Engineering, Computer Engineer or related equivalent</li> <li>At least 5 years of RTL design experience related to SOC/ASIC design</li> </ul> <p>&nbsp;</p> <p>The compensation range for this position is $160,000–$200,000. Salary ranges dependent on experience and location.</p>