Staff/Senior Hardware Engineer – Core Technology

Achronix Semiconductor

Posted March 13, 2024

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<div class="content-intro"><p>Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.</p></div> <h2 id="id-(62001042)Staff/SeniorHardwareEngineer(RTLDesign)CoreTechnology-JobDescription/Responsibilities">Job Description/Responsibilities</h2> <p>The successful candidate will be responsible for the development of high-performance digital logic used in standalone and embedded FPGAs. Primary focus is on designing and optimizing digital logic at the RTL level to meet functional and performance requirements.</p> <p>Responsibilities include the following:</p> <ul> <li>Work closely with system architects and/or customers to understand system-level requirements and translate them into RTL specifications</li> <li>Create and maintain design documentation, including specifications, test plans and design reviews</li> <li>Develop RTL code using Verilog/SystemVerilog to describe the behavior of digital circuits</li> <li>Optimize RTL code for area, power and performance while meeting design constraints</li> <li>Conduct CDC, sanity and lint checks to verify overall consistency and integrity</li> <li>Work with verification engineers to validate the design against functional and performance requirements, debug issues, report and track bugs to closure</li> <li>Work with backend engineers to develop synthesis constraints and assist with timing closure</li> <li>Assist in post-silicon bringup and validation</li> <li>Mentor junior engineers</li> </ul> <h2 id="id-(62001042)Staff/SeniorHardwareEngineer(RTLDesign)CoreTechnology-RequiredSkills">Required Skills</h2> <ul> <li>Experience designing and maintaining flows and methodologies from scratch</li> <li>Familiarity with ASIC design flow, including synthesis, timing closure, linting and CDC verification</li> <li>Proven experience in RTL design using Verilog/SystemVerilog</li> <li>Strong understanding of digital design principles, data path, control path, and finite state machines</li> <li>Proficiency in creating and using Makefiles</li> <li>Familiarity with using and/or designing FPGAs is a plus</li> <li>Familiarity with a scripting language (python or perl) is a plus</li> <li>Familiarity with version control systems (e.g., perforce, git) is a plus</li> <li>Excellent problem solving and debugging skills</li> <li>Well organized with strong communication and teamwork skills</li> </ul> <h2 id="id-(62001042)Staff/SeniorHardwareEngineer(RTLDesign)CoreTechnology-EducationandExperience">Education and Experience</h2> <ul> <li>BS/MS in Electrical Engineering or Computer Science + 2-10 years experience</li> </ul> <p>The compensation range for this position is $120,000–$190,000. Salary ranges dependent on experience and location.</p>