Verification Engineer
Achronix Semiconductor Corporation is a fabless semiconductor corporation based in Santa Clara, California, offering high-performance FPGA solutions. Achronix is the only supplier to have both high-performance and high-density standalone FPGAs and embedded FPGA (eFPGA) solutions in high-volume production. Achronix's FPGA and eFPGA IP offerings are further enhanced by ready-to-use PCIe accelerator cards targeting AI, ML, networking and data center applications. All of Achronix's products are supported by best-in-class EDA software tools.
Job Description/Responsibilities
The successful candidate will contribute to the verification and validation of FPGA cores and related ASIC subsystems implemented in modern FPGA technology nodes (7nm and below). Responsibilities include the following:
- Verify ASIC logic subsystems developed for high-speed networking and data center applications for inclusion in modern FPGAs
- Define, draft and review verification documents and testplans in collaboration with the design team
- Create automated processes for both block-level and system-level development and verification
- Implement functional coverage and enhance the testbench to ensure coverage closure
- Contribute to customer deliverables related to verification and device modeling
- Collaborate with internal and external team members on architectural decisions, development flows and methodologies
- Contribute to device bring-up and Post-Silicon validation
Required Skills
- Experience with modern pre-silicon verification techniques, especially including SystemVerilog, UVM, constraint-random and functional coverage methodologies
- Complete understanding of verification life cycle and ability to create and execute comprehensive verification plans
- Working knowledge of AXI, PCIe, CXL, Ethernet, DDR, or HBM
- Experience with scripting languages such as Python, Tcl, or Perl
- Strong technical writing and communication (verbal) skills
Preferred Skills
- Knowledge and familiarity with FPGA design flows including FPGA synthesis, place and route, timing closure, and debug tools
Education and Experience
- A minimum of 7 years experience.
- Bachelor or Master’s degree in Computer or Electrical Engineering.