ASIC Design Engineer - AI Engine
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
We are seeking a capable and motivated ASIC design engineer to be part of front-end design team of next generation AI Engine/ML silicon. You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.
This role will require deep understanding of design implementation and flows, tools and methodologies , including power intent UPF specifications.
THE PERSON:
Successful candidate will have an ASIC Design background/education, would have participated in silicon design projects as individual contributor and has a history of achieving results through effective execution
KEY RESPONISIBILITES:
- Design and micro-architecture of AI Engine building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
- RTL design and debug of relevant blocks to realize the low power architecture in silicon
- Analyze design metrics and make implementation choices to optimize PPA
- Work with verification and physical design teams to achieve high quality design and successful tape out
- Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features and/or algorithms
PREFERRED EXPERIENCES:
- Familiarity with ASIC design flow and academic or other experience with ASIC design
- Digital design and experience with RTL design in Verilog/System Verilog
- Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
- Low power digital design and analysis
- Low Power Design Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
- Circuit timing/STA, and practical experience with Prime Time or equivalent tools
- Understanding of FPGA architecture and implementation flow
- TCL, Perl, Python scripting
- Version control systems such as Perforce, ICManage or Git
- Strong verbal and written communication skills
- Ability to organize and present complex technical information
- Fluent in working with Linux environment
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-EM1
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
We are seeking a capable and motivated ASIC design engineer to be part of front-end design team of next generation AI Engine/ML silicon. You will take part in design and implementation of high-performance, low-power processor and accelerator IP for AI/ML applications.
This role will require deep understanding of design implementation and flows, tools and methodologies , including power intent UPF specifications.
THE PERSON:
Successful candidate will have an ASIC Design background/education, would have participated in silicon design projects as individual contributor and has a history of achieving results through effective execution
KEY RESPONISIBILITES:
- Design and micro-architecture of AI Engine building blocks and necessary infrastructure based on architecture, PPA, DFT, Functional Safety requirements
- RTL design and debug of relevant blocks to realize the low power architecture in silicon
- Analyze design metrics and make implementation choices to optimize PPA
- Work with verification and physical design teams to achieve high quality design and successful tape out
- Contribute in cross-functional teams to solve novel problems across multiple functional areas in development of required features and/or algorithms
PREFERRED EXPERIENCES:
- Familiarity with ASIC design flow and academic or other experience with ASIC design
- Digital design and experience with RTL design in Verilog/System Verilog
- Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
- Low power digital design and analysis
- Low Power Design Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
- Circuit timing/STA, and practical experience with Prime Time or equivalent tools
- Understanding of FPGA architecture and implementation flow
- TCL, Perl, Python scripting
- Version control systems such as Perforce, ICManage or Git
- Strong verbal and written communication skills
- Ability to organize and present complex technical information
- Fluent in working with Linux environment
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-EM1