ASIC Design Verification Co-op (4-months) - Ontario
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Location
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
This is a hybrid role (remote & in-office) as the hiring team will require the student to come to the Markham office approximately 2 days a week. COVID-19 protocols are being strictly followed.
Program Term
- This role is a 4-month
- January 8, 2024, to April 26, 2024
About the Department
An ASIC design and verification co-op engineering role in our System Management Unit (SMU) IP team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) silicon products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our design and verification engineers will work on block level functional design and verification and/or subsystem level integration and verification for a variety of embedded MP subsystems. Your contribution will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.
The Role
We are looking for a talented electrical or computer engineering student with strong academic records of relevant courses and projects in hardware logic design and computer architecture, above average capability of C/C++, Verilog or System Verilog programming, fast learning of technical concepts, and analytic thinking. A strong written and verbal communicator with excellent problem solving and attention to detail skills along with professional interpersonal communication capability.
What you’ll be doing
- Develop and refine MP subsystem design and verification workflow and methodology by creating and debugging automation scripts
- Set up and debug test regressions, analyze simulation results, resolve technical issues with design, verification teams
- Modify and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests
- Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology and C-DPI directed test methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
Requirements
- Completed 3 years of academic study in Electrical Engineering, Computer Engineering, or Computer Science with strong records in relevant technical courses and projects
- Excellent in programming using C/C++, one or more of Ruby, Perl, Python and Makefile
- Basic understanding of computer architecture, digital circuits and systems
- Basic knowledge about Verilog and System Verilog languages
- Basic knowledge about ASIC design & verification tools
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Location
1 Commerce Valley Dr E, Thornhill, ON L3T 7X6
This is a hybrid role (remote & in-office) as the hiring team will require the student to come to the Markham office approximately 2 days a week. COVID-19 protocols are being strictly followed.
Program Term
- This role is a 4-month
- January 8, 2024, to April 26, 2024
About the Department
An ASIC design and verification co-op engineering role in our System Management Unit (SMU) IP team, where a large number of individual embedded micro-processor (MP) subsystems and associated hardware accelerators vital to improve subsystems performance and functionality are designed and verified. These subsystem IPs provide high performance functions to System on Chip (SoC) silicon products across all AMD business units such as client computers, servers, discrete graphics, and gaming. Our design and verification engineers will work on block level functional design and verification and/or subsystem level integration and verification for a variety of embedded MP subsystems. Your contribution will impact security policy management, cryptography, data compression, high throughput DMA, power management, and many other subsystem applications.
The Role
We are looking for a talented electrical or computer engineering student with strong academic records of relevant courses and projects in hardware logic design and computer architecture, above average capability of C/C++, Verilog or System Verilog programming, fast learning of technical concepts, and analytic thinking. A strong written and verbal communicator with excellent problem solving and attention to detail skills along with professional interpersonal communication capability.
What you’ll be doing
- Develop and refine MP subsystem design and verification workflow and methodology by creating and debugging automation scripts
- Set up and debug test regressions, analyze simulation results, resolve technical issues with design, verification teams
- Modify and debug RTL designs using C-DPI directed test methodology, and/or using verification team’s testbenches and tests
- Develop and debug test plans using SystemVerilog/UVM constrained-random test methodology and C-DPI directed test methodology, and using object-oriented programming (OOP) techniques to implement/maintain testbenches and tests
Requirements
- Completed 3 years of academic study in Electrical Engineering, Computer Engineering, or Computer Science with strong records in relevant technical courses and projects
- Excellent in programming using C/C++, one or more of Ruby, Perl, Python and Makefile
- Basic understanding of computer architecture, digital circuits and systems
- Basic knowledge about Verilog and System Verilog languages
- Basic knowledge about ASIC design & verification tools