CPU Architecture Performance Modeling - SDE/MTS/SMTS
WHAT YOU DO AT AMD CHANGES EVERYTHING
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THE ROLE:
As member of CPU Architecture and Performance Modeling team you will be working on defining and evaluating the architecture of AMD’s next generation processors. You will be part of highly experienced and talented team of engineers working on processor performance modeling and microarchitecture development and will work closely with AMD's CPU and SOC performance architects.
THE PERSON:
A successful candidate will work with senior silicon design engineers, architects, RTL writers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
- Understanding architecture and micro-architecture features of AMD’s next generation processor Cores
- Coding and evaluating the performance of the features in simulator using C++
- Working with Architects/RTL team for optimizing and features for maximum performance gains
- Correlating the features on RTL
- Debugging of fails in simulation to understand the cause for performance changes/difference between RTL and simulator performance
- Involvement in defining new workloads to capture next generation real-world applications
PREFERRED EXPERIENCE:
- Strong knowledge of computer architecture with good experience of working and developing microarchitectural timing simulator, C++ programming.
- Knowledge of python or some other scripting language
- Knowledge of Verilog/VHDL
- x86 assembly language programming
ACADEMIC CREDENTIALS:
- Bachelor’s or master’s or PhD. degree in computer engineering/computer science
#LI-RR1
#LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
As member of CPU Architecture and Performance Modeling team you will be working on defining and evaluating the architecture of AMD’s next generation processors. You will be part of highly experienced and talented team of engineers working on processor performance modeling and microarchitecture development and will work closely with AMD's CPU and SOC performance architects.
THE PERSON:
A successful candidate will work with senior silicon design engineers, architects, RTL writers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
- Understanding architecture and micro-architecture features of AMD’s next generation processor Cores
- Coding and evaluating the performance of the features in simulator using C++
- Working with Architects/RTL team for optimizing and features for maximum performance gains
- Correlating the features on RTL
- Debugging of fails in simulation to understand the cause for performance changes/difference between RTL and simulator performance
- Involvement in defining new workloads to capture next generation real-world applications
PREFERRED EXPERIENCE:
- Strong knowledge of computer architecture with good experience of working and developing microarchitectural timing simulator, C++ programming.
- Knowledge of python or some other scripting language
- Knowledge of Verilog/VHDL
- x86 assembly language programming
ACADEMIC CREDENTIALS:
- Bachelor’s or master’s or PhD. degree in computer engineering/computer science
#LI-RR1
#LI-HYBRID