CPU Verification - SMTS Silicon Design Engineer
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SMTS SILICON DESIGN ENGINEER
THE ROLE:
The AMD Cores design & verification group develops high-end, next generation CPU’s that power different AMD SoC’s which are eventually set to change the course of how computing is visualized. The engineering teams are distributed across Canada, US and India. The CPU verification team in India is one of AMD India’s first teams & involved in contributing to the tape out of numerous AMD systems. As part of the CPU Design Verification team, our team will be responsible for the maintainability & scalability of RTL & testbench environment that is used for development & verification of the design. This is built up from basics like how workspaces are setup, how IPs are integrated and interacted in a System-On-Chip environment, how the tools/flows are developed to automate processes, and how tests are written and regressed. As always, the team is dedicated to coming up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.
THE PERSON:
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
Will work with different stake holders in getting a thorough understanding of high-level feature/s & get clarification(if any). Also evaluate cross-feature dependencies.
- After feature understanding, populate high level testplan that details out how we plan(Stimulus, debug, coverage) to verify the feature & what we cover/don’t cover as a part of the feature verification. Get it reviewed & incorporate feedback.
- Develop assembly(X86) level test cases to target the feature bringup. Debug fails(debug needs an understanding of computer architecture, micro-architecture & TB environment), file RTL/Verif bugs.
- After bringup completion, work on developing exerciser/random stimulus which help us evaluate cross-feature behavior by running regression. Debug if there are any fails.
- Ensure feature health is stable & in parallel work on evaluating stimulus coverage. If needed, tweak/add stimulus as appropriate.
- If the feature demands, then develop SV checker & SV coverpoints. All this while learning & understanding uarch is an integral part.
- Work on ensuring 100% FCOV that might involve developing new stimulus. Also it might demand working with other feature owners to close on cross-feature coverage. Work on microcode coverage.
- Interact with SoC folks & close on the SoC callout’s issued during testplanning.
- On a need basis, work on Post-Si bug recreation
PREFERRED EXPERIENCE:
- Good understanding about basics of computer architecture & digital systems.
- Good understanding of Verilog, System Verilog. Some knowledge of shell/perl scripting is a plus.
- Should be a good team player, quick thinker, pro-active, adaptable & outspoken/approachable.
- Must communicate well both written and orally
- Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks.
ACADEMIC CREDENTIALS:
- B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering
- 10+ years’ of experience in CPU verification.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
THE ROLE:
The AMD Cores design & verification group develops high-end, next generation CPU’s that power different AMD SoC’s which are eventually set to change the course of how computing is visualized. The engineering teams are distributed across Canada, US and India. The CPU verification team in India is one of AMD India’s first teams & involved in contributing to the tape out of numerous AMD systems. As part of the CPU Design Verification team, our team will be responsible for the maintainability & scalability of RTL & testbench environment that is used for development & verification of the design. This is built up from basics like how workspaces are setup, how IPs are integrated and interacted in a System-On-Chip environment, how the tools/flows are developed to automate processes, and how tests are written and regressed. As always, the team is dedicated to coming up with innovative solution to overcome new challenges related to specific project requirements and time-to-market.
THE PERSON:
A successful candidate will work with senior silicon design engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBLITIES:
Will work with different stake holders in getting a thorough understanding of high-level feature/s & get clarification(if any). Also evaluate cross-feature dependencies.
- After feature understanding, populate high level testplan that details out how we plan(Stimulus, debug, coverage) to verify the feature & what we cover/don’t cover as a part of the feature verification. Get it reviewed & incorporate feedback.
- Develop assembly(X86) level test cases to target the feature bringup. Debug fails(debug needs an understanding of computer architecture, micro-architecture & TB environment), file RTL/Verif bugs.
- After bringup completion, work on developing exerciser/random stimulus which help us evaluate cross-feature behavior by running regression. Debug if there are any fails.
- Ensure feature health is stable & in parallel work on evaluating stimulus coverage. If needed, tweak/add stimulus as appropriate.
- If the feature demands, then develop SV checker & SV coverpoints. All this while learning & understanding uarch is an integral part.
- Work on ensuring 100% FCOV that might involve developing new stimulus. Also it might demand working with other feature owners to close on cross-feature coverage. Work on microcode coverage.
- Interact with SoC folks & close on the SoC callout’s issued during testplanning.
- On a need basis, work on Post-Si bug recreation
PREFERRED EXPERIENCE:
- Good understanding about basics of computer architecture & digital systems.
- Good understanding of Verilog, System Verilog. Some knowledge of shell/perl scripting is a plus.
- Should be a good team player, quick thinker, pro-active, adaptable & outspoken/approachable.
- Must communicate well both written and orally
- Must be well-organized and should be able to multitask well with due diligence on closing his/her tasks.
ACADEMIC CREDENTIALS:
- B.E/B.Tech/M.E/M.Tech in Computer Science/Electrical/Electronic Engineering
- 10+ years’ of experience in CPU verification.