Design verification-4+ years
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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SENIOR SILICON DESIGN ENGINEER
THE ROLE:
As a member of the System IP Group, you will help bring to life cutting-edge designs. As a member of the front-end design integration/verification team, you will work closely with the architecture, IP design, SOC, and product engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will work with IP design and SOC DV engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBILITIES:
Integration and verification of complex System IP features.
Compose test plan and validation vectors to ensure functional completeness
Build test bench and monitors for DUT
Build C/C++/UVM model for simulation
Work closely with RTL designers and SOC team to scope out integration and verification requirements.
PREFERRED EXPERIENCE:
Prefer 10 or more years of experience in the ASIC design and verification industry. Should be familiar with industry standard integration flows.
Familiar with Linux Environment (including shell scripting and Linux GNU tools)
Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
Should be versatile in any one of the high-level verification flows such as SV, UVM, C++, etc., as well as knowledge of industry standard tools for verification
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
ACADEMIC CREDENTIALS:
- Bachelors or Master's degree in computer engineering/Electrical Engineering
#LI-ST1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SENIOR SILICON DESIGN ENGINEER
THE ROLE:
As a member of the System IP Group, you will help bring to life cutting-edge designs. As a member of the front-end design integration/verification team, you will work closely with the architecture, IP design, SOC, and product engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will work with IP design and SOC DV engineers. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills.
KEY RESPONSIBILITIES:
Integration and verification of complex System IP features.
Compose test plan and validation vectors to ensure functional completeness
Build test bench and monitors for DUT
Build C/C++/UVM model for simulation
Work closely with RTL designers and SOC team to scope out integration and verification requirements.
PREFERRED EXPERIENCE:
Prefer 10 or more years of experience in the ASIC design and verification industry. Should be familiar with industry standard integration flows.
Familiar with Linux Environment (including shell scripting and Linux GNU tools)
Experience with design for verification (assertion-based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
Should be versatile in any one of the high-level verification flows such as SV, UVM, C++, etc., as well as knowledge of industry standard tools for verification
Experience with VCS simulation tool, Perl/Shell scripting, and Verilog RTL design
ACADEMIC CREDENTIALS:
- Bachelors or Master's degree in computer engineering/Electrical Engineering
#LI-ST1