DFT PMTS Silicon Design Engineer
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AECG ASIC DFx - PMTS SILICON DESIGN ENGINEER
THE ROLE:
AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.
We are seeking a highly experienced DFT (Design for Test) Principal MTS to join our AECG SSD ASIC team in Bangalore. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of SoC design and development.
THE PERSON:
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
Lead DFT Strategy and Implementation
Develop and execute comprehensive DFT strategies for SoC projects, ensuring robust testability and manufacturability.
Develop and Optimize Test Architectures
Design and implement advanced test architectures, including scan insertion, BIST (Built-In Self-Test), LBIST (Logic Built-In Self-Test), and MBIST (Memory Built-In Self-Test), to enhance test coverage and efficiency.
Collaborate with Cross-Functional Team
Work closely with design, verification, and physical design teams to integrate DFT requirements seamlessly into the overall design process.
Lead Cross-Site Collaboration
Coordinate with teams across multiple locations to ensure cohesive and unified DFT strategies, promoting effective communication and collaboration.
Create and Validate Test Patterns
Generate and validate test patterns for both manufacturing and in-field testing, ensuring high-quality and reliable SoC.
Analyze and Debug Test Failures
Investigate and resolve test failures, providing innovative solutions to improve test coverage, yield, and overall product quality.
Conduct Post-Silicon Debugging
Perform post-silicon debugging to identify and rectify issues in manufactured silicon, ensuring optimal performance and reliability of SoC.
Mentor Junior Engineers
Provide guidance and mentorship to junior engineers, fostering their development in DFT techniques and best practices.
Stay Updated with Latest Technologies
Continuously monitor advancements in DFT technologies and methodologies, integrating cutting-edge solutions into the team's workflow.
Interface with External Vendors
Collaborate with external vendors and partners to ensure the successful integration of DFT solutions into the manufacturing process.
Research and Contribute to Patents
Engage in research activities, publish findings in reputable journals, and contribute to the development of patents in the field of SoC design and DFT methodologies
PREFERRED EXPERIENCE:
- Experience with industry-standard DFT tools and methodologies.
- Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc.
- Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
- Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
- Experience in solving logic design or timing issues with integration, synthesis and PD teams.
- Knowledge of semiconductor manufacturing processes.
- Familiarity with scripting languages such as Python, TCL or Perl.
- Experience with low-power design techniques.
- Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
- Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
- Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
- Excellent communication, management, and presentation skills.
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree or PhD degree in electrical engineering, Computer Engineering, or a related one.
- 16-20 years of experience in DFT, with a focus on SoC design.
- Proven track record of leading DFT projects from concept to production.
- Deep understanding of DFT techniques such as scan insertion, ATPG, BIST, LBIST, and MBIST.
- Strong problem-solving skills and ability to debug complex test issues.
- Excellent communication and leadership skills.
- Ability to work effectively in a collaborative team environment
#LI-RP1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AECG ASIC DFx - PMTS SILICON DESIGN ENGINEER
THE ROLE:
AECG SSD ASIC is a centralized ASIC design group within AMD’s Adaptive and Embedded Computing Organization. The group consists of design teams located in several AMD locations in North America and Asia. It is primarily responsible for architecture, design, and implementation of critical Design-for-Test (DFT) and Design-for-Debug (DFD) features for cutting edge AMD products.
We are seeking a highly experienced DFT (Design for Test) Principal MTS to join our AECG SSD ASIC team in Bangalore. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of SoC design and development.
THE PERSON:
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
Lead DFT Strategy and Implementation
Develop and execute comprehensive DFT strategies for SoC projects, ensuring robust testability and manufacturability.
Develop and Optimize Test Architectures
Design and implement advanced test architectures, including scan insertion, BIST (Built-In Self-Test), LBIST (Logic Built-In Self-Test), and MBIST (Memory Built-In Self-Test), to enhance test coverage and efficiency.
Collaborate with Cross-Functional Team
Work closely with design, verification, and physical design teams to integrate DFT requirements seamlessly into the overall design process.
Lead Cross-Site Collaboration
Coordinate with teams across multiple locations to ensure cohesive and unified DFT strategies, promoting effective communication and collaboration.
Create and Validate Test Patterns
Generate and validate test patterns for both manufacturing and in-field testing, ensuring high-quality and reliable SoC.
Analyze and Debug Test Failures
Investigate and resolve test failures, providing innovative solutions to improve test coverage, yield, and overall product quality.
Conduct Post-Silicon Debugging
Perform post-silicon debugging to identify and rectify issues in manufactured silicon, ensuring optimal performance and reliability of SoC.
Mentor Junior Engineers
Provide guidance and mentorship to junior engineers, fostering their development in DFT techniques and best practices.
Stay Updated with Latest Technologies
Continuously monitor advancements in DFT technologies and methodologies, integrating cutting-edge solutions into the team's workflow.
Interface with External Vendors
Collaborate with external vendors and partners to ensure the successful integration of DFT solutions into the manufacturing process.
Research and Contribute to Patents
Engage in research activities, publish findings in reputable journals, and contribute to the development of patents in the field of SoC design and DFT methodologies
PREFERRED EXPERIENCE:
- Experience with industry-standard DFT tools and methodologies.
- Experience in complex ASIC design (multi-million gates) in DFT/DFD techniques such as JTAG/IEEE standards, scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic, testing of high speed SerDes IO and analog design.
- Understanding various technologies that must work with DFT/DFD technology such as CPU’s, memory and I/O controllers, etc.
- Expertise in scan compression architecture, scan insertion and ATPG methodologies are essential.
- Working knowledge and experience in Verilog simulator and waveform debugging tools, proficiency in debugging both RTL and gate level simulations
- Experience in solving logic design or timing issues with integration, synthesis and PD teams.
- Knowledge of semiconductor manufacturing processes.
- Familiarity with scripting languages such as Python, TCL or Perl.
- Experience with low-power design techniques.
- Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: CPU or GPU, Memory sub-system, Fabrics, CPU/GPU coherency, Multimedia, I/O subsystems, Clocks, Resets, Virtualization and Security
- Experience analyzing CPU, GPU or System-level Micro-Architectural features to identify performance bottlenecks within different workloads
- Demonstrated expertise in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
- Excellent communication, management, and presentation skills.
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree or PhD degree in electrical engineering, Computer Engineering, or a related one.
- 16-20 years of experience in DFT, with a focus on SoC design.
- Proven track record of leading DFT projects from concept to production.
- Deep understanding of DFT techniques such as scan insertion, ATPG, BIST, LBIST, and MBIST.
- Strong problem-solving skills and ability to debug complex test issues.
- Excellent communication and leadership skills.
- Ability to work effectively in a collaborative team environment
#LI-RP1