Graphics Core IP Design Verification Engineer
Overview
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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Responsibilities
GRAPHICS CORE IP
THE TEAM:
Graphics Core IP is responsible for reading command packets that the graphics driver populates in memory, decoding them and then doing tessellation, lighting, rasterization, blending, depth detection, anti-aliasing amongst a variety of calculations to determine the final pixel color value that will be stored in memory, eventually to be read and displayed on a screen. We are also accelerating modern algorithms such as ray tracing and may be used for general compute, including ML/AI acceleration as well. Our team gets high level guidance from architecture and product definition teams, and then produces microarchitecture specifications, develops the design logic, and carries out the pre-silicon design verification until code freeze. In this capacity, we interact with architecture, physical design, project management, post-silicon bring-up and diagnostic teams, and occasionally software teams as well. Our team is not responsible for Physical Design, e.g. things such as placement and routing. However, we do closely work with PD to achieve things such as timing closure, area and power targets.
The Graphics Core IP hardware development department is more than 1,000 engineers spread across multiple different geographies. It has several different subsystem development teams, system level verification teams, physical design team as well as a graphics IP specific project management team. Needless to say, Graphics is one of the most valuable IPs that AMD owns and also one of the largest, most interesting and complex IPs in the GPU.
The immediate team is about 35 engineers across different levels of experience and we part of one of the subsystem development (digital design and verification) groups.
DESIGN VERIFICATION ENGINEER
THE ROLE:
As a Design Verification Engineer, you will work with leading industry tools and design/verification concepts to assist in developing the design, verification and infrastructure components of a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP) at AMD. You will work closely with senior design and verification engineers to help develop a testplan for pre-silicon Digital Design Verification, assist in the development of a testbench to exercise the design, develop test-cases based on the testplan and coverpoints/assertions to achieve verification closure. You will also manage, and monitor regression runs for different blocks, report bugs/failures that occur, and actively debug the failures found.
A project usually has a year timeline and there are many products that the GFXIP is deployed into, including main-stream, mobile, workstation, machine-intelligence GPUs, APUs and gaming consoles.
THE PERSON:
The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design and verification issue. You should be able strike a balance between collaborative problem-solving and independent solution development.
KEY RESPONSIBILITIES:
- Design Verification of digital design blocks:
- Study both high-level and micro architecture specifications and use Computer Architecture knowledge and background to gain an in depth understanding of new features or changes proposed in new projects.
- Create test plans that outlines required verification work for project.
- Produce verification code that tests RTL design functionality using UVM as per test plan.
- Write cover points to make sure verification items are properly exercised.
- Work on necessary debugging of verification code; fix tests to hit cover points if coverage is failing.
- Use Formal Verification techniques as needed.
- Manage and monitor regressions (regular repeated runs of same set of mostly random tests) for team’s blocks and fix errors in failing tests.
- Generate and analyze coverage reports to ensure exhaustive verification of the design and all possible end-cases.
- Write and edit csh, perl, python or ruby scripts to automate verification as needed.
- Regular review and sign-off of design verifcation work at key project milestones.
- Collaborate with other senior DV engineers in the team, Program Managers and mentor juniors, interns and new-hires
REQUIREMENTS:
- Solid fundamental understanding of Computer Architecture and Digital Design concepts.
- Strong background in OOP coding techniques.
- Experience with Verilog or SystemVerilog and UVM (preferred)
- Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.
- Strong analytical skills and attention to detail.
- Excellent written and verbal communication skills.
- Ability to solve problems independently along with great teamwork skills
GROWTH OPPORTUNITIES:
- Will get an understanding of how TLBs, data caches, data transfer protocols, data compression algorithms, threading, pipelining, timing analysis, and other computer architecture concepts are used in commercial ASIC design and verification.
- Opportunity to learn end to end Graphics Accelerator Pipeline and Graphics rendering concepts such as rasterization and ray tracing
- Will build expertise in Verilog, SystermVerilog, and OOP techniques used in complex design development.
- Universal Verification Methodology (UVM), and SystemVerilog Assertion Based Verifcation (ABV).
- Exposure to Formal Verification Techniques.
- Work with sophisticated industry standard tools such as Synopsys VCS, Verdi, VC Formal, etc.
- Be directly involved in the development of next-generation computer products.
- Develop communication skills further in a professional environment; meet and connect with industry experts and professionals
ACADEMIC CREDENTIALS:
- Bachelors or Masters Degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar
Qualifications
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
GRAPHICS CORE IP
THE TEAM:
Graphics Core IP is responsible for reading command packets that the graphics driver populates in memory, decoding them and then doing tessellation, lighting, rasterization, blending, depth detection, anti-aliasing amongst a variety of calculations to determine the final pixel color value that will be stored in memory, eventually to be read and displayed on a screen. We are also accelerating modern algorithms such as ray tracing and may be used for general compute, including ML/AI acceleration as well. Our team gets high level guidance from architecture and product definition teams, and then produces microarchitecture specifications, develops the design logic, and carries out the pre-silicon design verification until code freeze. In this capacity, we interact with architecture, physical design, project management, post-silicon bring-up and diagnostic teams, and occasionally software teams as well. Our team is not responsible for Physical Design, e.g. things such as placement and routing. However, we do closely work with PD to achieve things such as timing closure, area and power targets.
The Graphics Core IP hardware development department is more than 1,000 engineers spread across multiple different geographies. It has several different subsystem development teams, system level verification teams, physical design team as well as a graphics IP specific project management team. Needless to say, Graphics is one of the most valuable IPs that AMD owns and also one of the largest, most interesting and complex IPs in the GPU.
The immediate team is about 35 engineers across different levels of experience and we part of one of the subsystem development (digital design and verification) groups.
DESIGN VERIFICATION ENGINEER
THE ROLE:
As a Design Verification Engineer, you will work with leading industry tools and design/verification concepts to assist in developing the design, verification and infrastructure components of a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP) at AMD. You will work closely with senior design and verification engineers to help develop a testplan for pre-silicon Digital Design Verification, assist in the development of a testbench to exercise the design, develop test-cases based on the testplan and coverpoints/assertions to achieve verification closure. You will also manage, and monitor regression runs for different blocks, report bugs/failures that occur, and actively debug the failures found.
A project usually has a year timeline and there are many products that the GFXIP is deployed into, including main-stream, mobile, workstation, machine-intelligence GPUs, APUs and gaming consoles.
THE PERSON:
The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design and verification issue. You should be able strike a balance between collaborative problem-solving and independent solution development.
KEY RESPONSIBILITIES:
- Design Verification of digital design blocks:
- Study both high-level and micro architecture specifications and use Computer Architecture knowledge and background to gain an in depth understanding of new features or changes proposed in new projects.
- Create test plans that outlines required verification work for project.
- Produce verification code that tests RTL design functionality using UVM as per test plan.
- Write cover points to make sure verification items are properly exercised.
- Work on necessary debugging of verification code; fix tests to hit cover points if coverage is failing.
- Use Formal Verification techniques as needed.
- Manage and monitor regressions (regular repeated runs of same set of mostly random tests) for team’s blocks and fix errors in failing tests.
- Generate and analyze coverage reports to ensure exhaustive verification of the design and all possible end-cases.
- Write and edit csh, perl, python or ruby scripts to automate verification as needed.
- Regular review and sign-off of design verifcation work at key project milestones.
- Collaborate with other senior DV engineers in the team, Program Managers and mentor juniors, interns and new-hires
REQUIREMENTS:
- Solid fundamental understanding of Computer Architecture and Digital Design concepts.
- Strong background in OOP coding techniques.
- Experience with Verilog or SystemVerilog and UVM (preferred)
- Familiarity with scripting languages: perl or tcl or ruby or Bash or python, etc.
- Strong analytical skills and attention to detail.
- Excellent written and verbal communication skills.
- Ability to solve problems independently along with great teamwork skills
GROWTH OPPORTUNITIES:
- Will get an understanding of how TLBs, data caches, data transfer protocols, data compression algorithms, threading, pipelining, timing analysis, and other computer architecture concepts are used in commercial ASIC design and verification.
- Opportunity to learn end to end Graphics Accelerator Pipeline and Graphics rendering concepts such as rasterization and ray tracing
- Will build expertise in Verilog, SystermVerilog, and OOP techniques used in complex design development.
- Universal Verification Methodology (UVM), and SystemVerilog Assertion Based Verifcation (ABV).
- Exposure to Formal Verification Techniques.
- Work with sophisticated industry standard tools such as Synopsys VCS, Verdi, VC Formal, etc.
- Be directly involved in the development of next-generation computer products.
- Develop communication skills further in a professional environment; meet and connect with industry experts and professionals
ACADEMIC CREDENTIALS:
- Bachelors or Masters Degree in Computer, Electrical, Mechatronics Engineering or Engineering Science or similar