IP Design Verification Engineer (7+ years)

Advanced Micro Devices Inc

Bangalore, India

Verilog System Verilog

Posted Sept. 13, 2023

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WHAT YOU DO AT AMD CHANGES EVERYTHING

We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives. 

AMD together we advance_

KEY RESPONSIBILITIES:

• Developing test plans
• Coding and bring up of asm, c++ tests.
• UVM test bench components coding and maintaining.
• Debugging regression fails
• Functional coverage, code coverage closure

PREFERRED EXPERIENCE:

• Should have worked on IP level verification.
• Hands on experience with UVM, SV, C++
• Experience in developing complex test bench/model in UVM, Verilog, System Verilog
• Hands on experience in developing test plans, coverage closure.
• Ability to code readable, maintainable and verifiable code using UVM, SV, C++
• Strong digital design concepts
• Experience in developing asm tests will be an added advantage.
• Experience in Power Management, Clock, Reset will be an added advantage.
• Experience/Knowledge in processor-based systems/sub system/IP Verification will be an added advantage
• Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage.

#LI-ST1

#HYBRID

KEY RESPONSIBILITIES:

• Developing test plans
• Coding and bring up of asm, c++ tests.
• UVM test bench components coding and maintaining.
• Debugging regression fails
• Functional coverage, code coverage closure

PREFERRED EXPERIENCE:

• Should have worked on IP level verification.
• Hands on experience with UVM, SV, C++
• Experience in developing complex test bench/model in UVM, Verilog, System Verilog
• Hands on experience in developing test plans, coverage closure.
• Ability to code readable, maintainable and verifiable code using UVM, SV, C++
• Strong digital design concepts
• Experience in developing asm tests will be an added advantage.
• Experience in Power Management, Clock, Reset will be an added advantage.
• Experience/Knowledge in processor-based systems/sub system/IP Verification will be an added advantage
• Experience/Knowledge DPI Interface, Ruby/Perl script programming skills will be an added advantage.

#LI-ST1

#HYBRID