ISP Silicon Design Verification Engineer (DV)
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At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
AMD Image Signal Processor (ISP) team is looking for a staff engineer responsible for IP verification work for AMD future products. He/she will be a key technical member in the verification team and co-work with different functional teams (Architect, Algorithm, Design, Verification, Firmware, etc.) to deliver AMD ISP subsystem designs to SoC. He/she will have the opportunity to work with the global teams to develop a chip from end to end and touch industry-advanced design flows, methodologies, and knowledge.
THE PERSON:
The successful candidate would be hired as staff engineer level, with the expectation that they would have minimal 3-5 years of verification experience in the multimedia, image processing or similar industry. A candidate that has a strong image science background with a focus on image signal processing (ISP) is highly desirable.
KEY RESPONSIBLITIES:
- Understand ISP hardware architecture and functional block being designed
- Build C/C++ model for simulation, build test bench and monitors for block test environment
- Participate in block level and IP subsystem level verification work, simulate and debug the codes in coding stage
- Compose ASIC specific part of test plan, work with algorithm, firmware and FPGA engineers to prove functional correctness from block level to IP subsystem level
- Support camera SW, FW and diagnostics team for pre-silicon and post-silicon debugging
- Maintain verification environment, solve flow issues, and develop scripts to improve flow efficiency.
- Collaborate and interface with local and global management to make accountable deliverables on time
PREFERRED EXPERIENCE:
- BS-CS/BS-EE with at least 10 years' experience or MS with at least 8 years' experience in ASIC/SoC verification
- Hand-on experience in all domains of complex ASIC DV flow from plan to coverage
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Good knowledge on verification methodologies like UVM is a big plus
- Good knowledge of multimedia/video/camera related image processing
- Experience in power-aware verification is an asset
- Strong individual analysis, problem solving skills and teamwork attitude
- Will be a plus if having FPGA validation experience
- Experience of working with multi-site teams is preferred
ACADEMIC CREDENTIALS:
- Bachelor or Master, major in EE, CS or related area
LOCATION:
- Hsinchu, Taiwan
#LI-VJ1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
AMD Image Signal Processor (ISP) team is looking for a staff engineer responsible for IP verification work for AMD future products. He/she will be a key technical member in the verification team and co-work with different functional teams (Architect, Algorithm, Design, Verification, Firmware, etc.) to deliver AMD ISP subsystem designs to SoC. He/she will have the opportunity to work with the global teams to develop a chip from end to end and touch industry-advanced design flows, methodologies, and knowledge.
THE PERSON:
The successful candidate would be hired as staff engineer level, with the expectation that they would have minimal 3-5 years of verification experience in the multimedia, image processing or similar industry. A candidate that has a strong image science background with a focus on image signal processing (ISP) is highly desirable.
KEY RESPONSIBLITIES:
- Understand ISP hardware architecture and functional block being designed
- Build C/C++ model for simulation, build test bench and monitors for block test environment
- Participate in block level and IP subsystem level verification work, simulate and debug the codes in coding stage
- Compose ASIC specific part of test plan, work with algorithm, firmware and FPGA engineers to prove functional correctness from block level to IP subsystem level
- Support camera SW, FW and diagnostics team for pre-silicon and post-silicon debugging
- Maintain verification environment, solve flow issues, and develop scripts to improve flow efficiency.
- Collaborate and interface with local and global management to make accountable deliverables on time
PREFERRED EXPERIENCE:
- BS-CS/BS-EE with at least 10 years' experience or MS with at least 8 years' experience in ASIC/SoC verification
- Hand-on experience in all domains of complex ASIC DV flow from plan to coverage
- Experience with design for verification (assertion based design strategies, code coverage, functional coverage, test plan, gate-level simulation, back-annotation etc.)
- Good knowledge on verification methodologies like UVM is a big plus
- Good knowledge of multimedia/video/camera related image processing
- Experience in power-aware verification is an asset
- Strong individual analysis, problem solving skills and teamwork attitude
- Will be a plus if having FPGA validation experience
- Experience of working with multi-site teams is preferred
ACADEMIC CREDENTIALS:
- Bachelor or Master, major in EE, CS or related area
LOCATION:
- Hsinchu, Taiwan
#LI-VJ1