MTS Engineer

Advanced Micro Devices Inc

Hyderabad, India

Verilog FPGA ASIC RTL

Posted April 19, 2024

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MTS Silicon Design Engineer

THE ROLE: 

MTS Silicon Design engineer in the FPGA architecture team

THE PERSON: 

You have a passion for modern VLSI architectures, digital design, digital circuits, low power  and algorithms in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES: 

• Work in the area of circuits, physical architecture, power and algorithms related to existing and future FPGA architecture
• Responsible for aspects like physical architectural modeling, power-performance modeling and architectural/circuit exploration, circuit simulations, improving design methodologies for FPGA design flows

PREFERRED EXPERIENCE: 

• Experienced with 4-10 years of experience
• Experience in digital logic design, FPGA/ASIC synthesis/implementation flows
• Skilled in Static Timing Analysis (STA) and comfortable in working with FPGA/ASIC timing tools (Vivado/Quartus/Primetime/Tempus)
• Preferred (additional) skills
  • Experience in RTL design, functional-sims using Verilog/System-Verilog
  • Power analysis and optimization using FPGA/ASIC flows
  • Concepts of low power optimization
  • Experience or familiarity with basics of circuit design, CMOS transistor design, digital design using Verilog
• Good scripting skills with Python and basics of statistics and data analysis

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-NS2

MTS Silicon Design Engineer

THE ROLE: 

MTS Silicon Design engineer in the FPGA architecture team

THE PERSON: 

You have a passion for modern VLSI architectures, digital design, digital circuits, low power  and algorithms in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems. 

KEY RESPONSIBILITIES: 

• Work in the area of circuits, physical architecture, power and algorithms related to existing and future FPGA architecture
• Responsible for aspects like physical architectural modeling, power-performance modeling and architectural/circuit exploration, circuit simulations, improving design methodologies for FPGA design flows

PREFERRED EXPERIENCE: 

• Experienced with 4-10 years of experience
• Experience in digital logic design, FPGA/ASIC synthesis/implementation flows
• Skilled in Static Timing Analysis (STA) and comfortable in working with FPGA/ASIC timing tools (Vivado/Quartus/Primetime/Tempus)
• Preferred (additional) skills
  • Experience in RTL design, functional-sims using Verilog/System-Verilog
  • Power analysis and optimization using FPGA/ASIC flows
  • Concepts of low power optimization
  • Experience or familiarity with basics of circuit design, CMOS transistor design, digital design using Verilog
• Good scripting skills with Python and basics of statistics and data analysis

ACADEMIC CREDENTIALS: 

• Bachelors or Masters degree in computer engineering/Electrical Engineering

#LI-NS2