MTS Silicon Design Engineer AECG ASIC Physical Design Lead
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MTS SILICON DESIGN ENGINEER
THE ROLE:
The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements.
THE PERSON:
AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions.
KEY RESPONSIBLITIES:
- Engineer leading SIGNOFF (FCT, IR/EM,power profiling, RDL) teams improvements in both pre-silicon and post-silicon design phase
- Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off
- Lead internal and external teams to deliver best in class performance/watt/mm^2
- Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
- Drive and hands-on flow development and scripting
- Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high-performance ASICs
PREFERRED EXPERIENCE:
- Strong understanding of development of custom ASICs for external customers.
- Strong background in physical design with exposure to circuit and logic design.
- Proven track record of delivering SOCs in process technologies 7nm and below.
- Expert user of P&R, Timing and Physical verification tools from top EDA vendors.
- Proven expertise in developing physical implementation flows as required.
- Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design.
- Experience in leading a small team of high performing individuals.
- Excellent analytical and problem-solving skills along with attention to details
- Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
- Knowledge of Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations will be plus
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player
ACADEMIC CREDENTIALS:
- BS or MS degree in in Electronics/Electrical Engineering. 10+years of experience in physical design role leading to an understanding of RTL to GDS development.
#LI-SR4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS SILICON DESIGN ENGINEER
THE ROLE:
The focus of this role in the AECG ASIC organization is to lead physical design for next generation ASICs that meet Engineering, Business and Customer requirements.
THE PERSON:
AMD is looking for an engineering leader passionate about driving the best Power Performance Area (PPA) of ASIC solutions for AECG customers. The ideal candidate will have proven experience in driving physical design optimization to deliver industry leading performance/area and performance/power. In this role the candidate will work with the customer, SOC architects, the CAD team and the design team and drive floorplanning and physical design flows for best in class ASIC solutions.
KEY RESPONSIBLITIES:
- Engineer leading SIGNOFF (FCT, IR/EM,power profiling, RDL) teams improvements in both pre-silicon and post-silicon design phase
- Tasks to include Full Chip Level Floor planning, Bus / Pin Planning, feed-thru planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, Physical Verification and Sign Off
- Lead internal and external teams to deliver best in class performance/watt/mm^2
- Identify complex technical problems, break them down, summarize multiple possible solutions, and lead the team in the right direction
- Drive and hands-on flow development and scripting
- Drive silicon correlation and deliver systematic improvements to improve silicon to STA on high-performance ASICs
PREFERRED EXPERIENCE:
- Strong understanding of development of custom ASICs for external customers.
- Strong background in physical design with exposure to circuit and logic design.
- Proven track record of delivering SOCs in process technologies 7nm and below.
- Expert user of P&R, Timing and Physical verification tools from top EDA vendors.
- Proven expertise in developing physical implementation flows as required.
- Ability to co-optimize and make appropriate tradeoff across architecture, front-end design, and back-end design.
- Experience in leading a small team of high performing individuals.
- Excellent analytical and problem-solving skills along with attention to details
- Strong Timing closure skills including signal integrity, RC extraction, Clock tree synthesis, and library understanding
- Knowledge of Top level Floor planning, Partitioning, Pin Placement, Reuse Block Planning, Full chip clock planning for top level mesh and clock stations will be plus
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- Ability to provide mentorship and guidance to junior and senior engineers, and be an effective team player
ACADEMIC CREDENTIALS:
- BS or MS degree in in Electronics/Electrical Engineering. 10+years of experience in physical design role leading to an understanding of RTL to GDS development.
#LI-SR4