MTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
DCGPU Root Port IP DV Engineer
THE ROLE:
We’re a group of passionate and innovative engineers, who are working on implement cutting edge interconnection technology into world leading x86 SoC solution, like Ryzen/Epyc/Radeon/Instinct family. As the whole industry is going through the Data Centric computing era, high throughout and low latency interconnection becomes more and more critical, this makes our team key to AMD’s future roadmap and success.
AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of becoming part of a world class team. In this role you will have an opportunity to participate in the world’s state-of-the-art technology execution, since what we are working on will be a part of AMD’s Data Center GPU development.
THE PERSON:
Be good at communication and teamwork, self-motivated and with good work ethics.
KEY RESPONSIBILITIES:
- DCGPU Root IP test-bench maintenance and updating, to support new feature.
- Long lead interconnection IP/Subsystem/Combo-Whacker level test-bench building, test-case debugging.
- Long lead interconnection IP and PCIe IP validation support.
- Verification environment efficiency improvement.
PREFERRED EXPERIENCE:
- Deep understanding of PCIe (PCI-Express) protocol (especially Transaction layer) and experience on PCIe Design/Verification and Debug.
- Good RTL coding with Verilog, test-bench coding with SystemVerilog.
- Good knowledge of design verification methodology, familiar with UVM/OVM/VMM.
- Good understanding of ASIC/SoC design and verification flow.
- Good knowledge about computer architecture and CPU/GPU micro-architecture, know ‘how’ the whole system works.
- Have at least two kinds of following knowledge: CXL, AMBA AXI/AHB/APB, 802.3 Ethernet Protocol.
- Have low power or power aware experience is a strong plus.
- Be good at script language, such as Perl, Python, Ruby, C Shell, Makefile.
- Be good at both speaking and written English.
- Strong problem shooting capability and uncompromising delivery mindset.
- Willingness of driving challenging tasks to closure.
- Experience of collaboration with global team with different time zones and background.
ACADEMIC CREDENTIALS:
- Preferred EE/CS of related MSEE with minimum 5 years, or BSEE with minimum 7 years of ASIC/SoC verification experience.
LOCATION: Shanghai
#LI-JG2 #LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
DCGPU Root Port IP DV Engineer
THE ROLE:
We’re a group of passionate and innovative engineers, who are working on implement cutting edge interconnection technology into world leading x86 SoC solution, like Ryzen/Epyc/Radeon/Instinct family. As the whole industry is going through the Data Centric computing era, high throughout and low latency interconnection becomes more and more critical, this makes our team key to AMD’s future roadmap and success.
AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of becoming part of a world class team. In this role you will have an opportunity to participate in the world’s state-of-the-art technology execution, since what we are working on will be a part of AMD’s Data Center GPU development.
THE PERSON:
Be good at communication and teamwork, self-motivated and with good work ethics.
KEY RESPONSIBILITIES:
- DCGPU Root IP test-bench maintenance and updating, to support new feature.
- Long lead interconnection IP/Subsystem/Combo-Whacker level test-bench building, test-case debugging.
- Long lead interconnection IP and PCIe IP validation support.
- Verification environment efficiency improvement.
PREFERRED EXPERIENCE:
- Deep understanding of PCIe (PCI-Express) protocol (especially Transaction layer) and experience on PCIe Design/Verification and Debug.
- Good RTL coding with Verilog, test-bench coding with SystemVerilog.
- Good knowledge of design verification methodology, familiar with UVM/OVM/VMM.
- Good understanding of ASIC/SoC design and verification flow.
- Good knowledge about computer architecture and CPU/GPU micro-architecture, know ‘how’ the whole system works.
- Have at least two kinds of following knowledge: CXL, AMBA AXI/AHB/APB, 802.3 Ethernet Protocol.
- Have low power or power aware experience is a strong plus.
- Be good at script language, such as Perl, Python, Ruby, C Shell, Makefile.
- Be good at both speaking and written English.
- Strong problem shooting capability and uncompromising delivery mindset.
- Willingness of driving challenging tasks to closure.
- Experience of collaboration with global team with different time zones and background.
ACADEMIC CREDENTIALS:
- Preferred EE/CS of related MSEE with minimum 5 years, or BSEE with minimum 7 years of ASIC/SoC verification experience.
LOCATION: Shanghai
#LI-JG2 #LI-HYBRID