MTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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MTS SILICON DESIGN ENGINEER
THE ROLE:
Candidate should have worked on complex design with hands on experience in developing testbench, UVC, test-planning and execute test plan, coverage development and closure. Candidate actively involve in technical discussion and test plan review.
THE PERSON:
Experience requires demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage.
Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
Experience or exposure to UVM/OVM is a must.
Must demonstrate strong Object Oriented programing skills and concepts.
Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is a plus
Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.
KEY RESPONSIBILITIES:
- Work with all stakeholders such as design architect and block designer to understand features to be verified. Follow the process and good practices to develop UVC and testbench for design verification.
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Proficient in debugging RTL code using simulation tools
- Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is added advantage
- ASIC design verification experience with 8 to 10 years
- Hands on experience in developing complex UVC
- Good debugging skill and good knowledge of verification tool and methodology
- Hands on experience with coverage planning, coding, and coverage closure
- Should have worked on developing testplan at module level/IP level /Chip-level project
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Desirable assets with prior exposure to DDR/LPDDR, DFI specifications.
ACADEMIC CREDENTIALS:
- B.E/B.Tech in ECE, Electrical engineering degree or Master’s degree preferred with emphasis in Electrical/Electronics Engineering. Preferred VLSI major in post-graduation
#LI-ST1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS SILICON DESIGN ENGINEER
THE ROLE:
Candidate should have worked on complex design with hands on experience in developing testbench, UVC, test-planning and execute test plan, coverage development and closure. Candidate actively involve in technical discussion and test plan review.
THE PERSON:
Experience requires demonstrated technical expertise in functional verification of complex designs including: test planning, test bench development, stimulus generation, checking, and functional coverage.
Experience or exposure to Verilog, System Verilog, Object Oriented Programming/C++, Perl, and logic simulation is a requirement
Experience or exposure to UVM/OVM is a must.
Must demonstrate strong Object Oriented programing skills and concepts.
Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is a plus
Requires strong communication skills and the ability to work independently as well as in a cross-site team environment.
KEY RESPONSIBILITIES:
- Work with all stakeholders such as design architect and block designer to understand features to be verified. Follow the process and good practices to develop UVC and testbench for design verification.
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements.
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Proficient in debugging RTL code using simulation tools
- Experience with memory controllers, dfi, dram memory models(ddr4/5, lpddr4/5, hbm, NVDIMM) and/or ddr phys is added advantage
- ASIC design verification experience with 8 to 10 years
- Hands on experience in developing complex UVC
- Good debugging skill and good knowledge of verification tool and methodology
- Hands on experience with coverage planning, coding, and coverage closure
- Should have worked on developing testplan at module level/IP level /Chip-level project
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Desirable assets with prior exposure to DDR/LPDDR, DFI specifications.
ACADEMIC CREDENTIALS:
- B.E/B.Tech in ECE, Electrical engineering degree or Master’s degree preferred with emphasis in Electrical/Electronics Engineering. Preferred VLSI major in post-graduation
#LI-ST1