MTS Silicon Design Engineer
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MTS SILICON DESIGN ENGINEER
THE ROLE:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, and capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
KEY RESPONSIBILITIES:
The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader. The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
PREFERRED EXPERIENCE:
The candidate must have:
- Deep understanding on ASIC/SOC design flow
- Excellent knowledge of design verification methodology, such as VMM or OVM.
- Solid experiences with simulation model creation and the testbench build
- Strong RTL coding with Verilog
- Strong C/C++ software development experiences
- Be good at scripting language, such as Perl, C shell, Makefile.
ACADEMIC CREDENTIALS:
MSEE with a minimum of 9 years, or BSEE with a minimum of 11 years’ experience in digital ASIC/SOC design verification
perform and improve pre-silicon verification quality and product Time to Market for Southbridge
- Provide the technical leadership to the DV team for the new Southbridge project
- Work independently on various DV tasks and providing technical guidance to the DV team.
- Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
PREFERRED EXPERIENCE:
- Master in Electrical Engineering, Computer Science or related
- Good understanding on ASIC design verification flow
- RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
- Knowledge on Perl, OVL, SVA, SV, UVM, OVM, script programming etc.
- USB experiences is a plus
ACADEMIC CREDENTIALS:
MSEE with minimum of 9 years, or BSEE with minimum of 11 years experiences in digital ASIC/SOC design verification
#LI-SC1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
MTS SILICON DESIGN ENGINEER
THE ROLE:
It is a must that the candidate has one or more of the following experience/knowledge, such as X86/ARM/8051 architecture, AMBA(AXI/AHB/APB) bus, USB(3.0/2.0/1.1; HSIC/host/device/OTG) system, NAND Flash host controller/BCH/double-data-rate interface, PCI-E/PCI bus, low power design, clock generation and control, SD/eMMC host controller, SATA/SAS, Legacy IPs (SPI/SMBUS/ACPI/LPC/GPIO), General connectivity IPs (I2S/I2C/UART), Ethernet, JTAG, etc.
THE PERSON:
The candidate is expected to exhibit good verbal and written communication skills in both Chinese and English, specialized knowledge plus broad technical knowledge outside his or her area of expertise, driving execution of quality and timely project performance, and capability to solve complex, novel and no-recurring problems, capability to initiate significant changes and lead development & implementation, and decision-making on most critical technical areas.
KEY RESPONSIBILITIES:
The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader. The successful candidate will work with team members and apply current functional verification techniques to perform and improve pre-silicon verification quality and product Time to Market for ASIC/SOC projects. The role will include technical leading on multiple products or product line, coaching and mentoring less experienced staff and influencing others as a strong technical leader.
PREFERRED EXPERIENCE:
The candidate must have:
- Deep understanding on ASIC/SOC design flow
- Excellent knowledge of design verification methodology, such as VMM or OVM.
- Solid experiences with simulation model creation and the testbench build
- Strong RTL coding with Verilog
- Strong C/C++ software development experiences
- Be good at scripting language, such as Perl, C shell, Makefile.
ACADEMIC CREDENTIALS:
MSEE with a minimum of 9 years, or BSEE with a minimum of 11 years’ experience in digital ASIC/SOC design verification
perform and improve pre-silicon verification quality and product Time to Market for Southbridge
- Provide the technical leadership to the DV team for the new Southbridge project
- Work independently on various DV tasks and providing technical guidance to the DV team.
- Be involved technically in the porting/creation of the DV environment for the new design, block and chip level test plan creation and implementation, coverage analysis, and regression cleanup
PREFERRED EXPERIENCE:
- Master in Electrical Engineering, Computer Science or related
- Good understanding on ASIC design verification flow
- RTL coding with Verilog/System Verilog and familiar with front-end design flow and C/C++ programming experiences
- Knowledge on Perl, OVL, SVA, SV, UVM, OVM, script programming etc.
- USB experiences is a plus
ACADEMIC CREDENTIALS:
MSEE with minimum of 9 years, or BSEE with minimum of 11 years experiences in digital ASIC/SOC design verification
#LI-SC1