PMTS Hardware Development Eng.
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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THE ROLE:
An experienced Pre-Silicon Verification engineer to lead the verification strategy and methodology of our High-Speed IO End Point (EP) Devices for next-generation Server SoC products. This position is integral to the execution and roadmap of our test card strategy and implementation.
THE PERSON:
The ideal candidate will work closely with cross-functional teams, demonstrating excellent communication skills, leadership, and problem-solving abilities. Detail-oriented and adaptable, they will drive tasks to completion with high quality and collaborate with global teams. Combining specialized knowledge and broad technical expertise, the candidate will tackle complex, novel challenges, and be self-motivated, consistently performing at the highest technical capacity, delivering timely results, and making critical decisions.
KEY RESPONSIBILITIES:
- Lead collaboration with cross-functional team, architects, and designers to understand the IP features and High-Speed IO EP devices.
- Verification of critical high-speed digital designs using test bench components, test and sequence libraries with UVM
- Develop and implement Pre-Silicon Verification Test Plans.
- Verification of critical high-speed digital designs using coverage-driven random, directed testing techniques, and Formal verification.
- Drive debug and root-cause analysis for PCIe and other High-Speed IO protocols for SoC related issues.
PREFERRED EXPERIENCE
- Expertise in SystemVerilog and UVM methodologies
- Proficient in scripting languages, including Bash, Python, and Perl
- Comprehensive understanding of PCIe protocol and familiarity with CXL is a plus
- In-depth knowledge of cache coherency protocols and their system-level interactions
- Excellent grasp of standard bus/interface protocols, such as AXI, PIPE, etc.
- Strong communication, time management, and presentation abilities
- Strong Experience in developing pre-silicon verification methodologies and infrastructure
- Ability to multitask, manage priorities, and adapt to changing project needs
- Knowledge in using verification tools and simulators like VCS, Cadence, or Synopsys
- 10+ years of experience
ACADEMIC CREDENTIALS:
- Bachelor’s degree or higher in Electrical/Computer Engineering or Electronics / Computer Science related.
LOCATION:
Penang, Malaysia
#LI-FY
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
An experienced Pre-Silicon Verification engineer to lead the verification strategy and methodology of our High-Speed IO End Point (EP) Devices for next-generation Server SoC products. This position is integral to the execution and roadmap of our test card strategy and implementation.
THE PERSON:
The ideal candidate will work closely with cross-functional teams, demonstrating excellent communication skills, leadership, and problem-solving abilities. Detail-oriented and adaptable, they will drive tasks to completion with high quality and collaborate with global teams. Combining specialized knowledge and broad technical expertise, the candidate will tackle complex, novel challenges, and be self-motivated, consistently performing at the highest technical capacity, delivering timely results, and making critical decisions.
KEY RESPONSIBILITIES:
- Lead collaboration with cross-functional team, architects, and designers to understand the IP features and High-Speed IO EP devices.
- Verification of critical high-speed digital designs using test bench components, test and sequence libraries with UVM
- Develop and implement Pre-Silicon Verification Test Plans.
- Verification of critical high-speed digital designs using coverage-driven random, directed testing techniques, and Formal verification.
- Drive debug and root-cause analysis for PCIe and other High-Speed IO protocols for SoC related issues.
PREFERRED EXPERIENCE
- Expertise in SystemVerilog and UVM methodologies
- Proficient in scripting languages, including Bash, Python, and Perl
- Comprehensive understanding of PCIe protocol and familiarity with CXL is a plus
- In-depth knowledge of cache coherency protocols and their system-level interactions
- Excellent grasp of standard bus/interface protocols, such as AXI, PIPE, etc.
- Strong communication, time management, and presentation abilities
- Strong Experience in developing pre-silicon verification methodologies and infrastructure
- Ability to multitask, manage priorities, and adapt to changing project needs
- Knowledge in using verification tools and simulators like VCS, Cadence, or Synopsys
- 10+ years of experience
ACADEMIC CREDENTIALS:
- Bachelor’s degree or higher in Electrical/Computer Engineering or Electronics / Computer Science related.
LOCATION:
Penang, Malaysia
#LI-FY
#LI-Hybrid