Pre-Silicon Design Verification Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As a Design Verification Engineer, you will work with leading industry tools and design/verification concepts to assist in developing the design, verification and infrastructure components of a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP) at AMD. You will work closely with senior design and verification engineers to help develop a testplan for pre-silicon Digital Design Verification, assist in the development of a testbench to exercise the design, develop test-cases based on the testplan and coverpoints/assertions to achieve verification closure. You will also manage, and monitor regression runs for different blocks, report bugs/failures that occur, and actively debug the failures found.
THE PERSON:
The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design and verification issue. You should be able strike a balance between collaborative problem-solving and independent solution development.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, and other DV engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Develop directed and random verification tests
- Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any test issues
- Develop functional coverage properties as needed
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE:
- Solid fundamental understanding of Computer Architecture and Digital Design concepts
- Proficient in IP level ASIC verification
- Proficient in debugging DV and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux environments
- Experienced with Verilog, System Verilog, C, and C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment, e.g. scripting
- Exposure to simulation profile, efficiency improvement, acceleration
- Excellent understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Graphics pipeline knowledge is an asset
- Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer Engineering/Electrical Engineering or Engineering Science or similar
This role is not eligible for visa sponsorship.
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
AMD may use Artificial Intelligence to help screen, assess or select applicants for this position. AMD’s “Responsible AI Policy” is available here.
This posting is for an existing vacancy.
THE ROLE:
As a Design Verification Engineer, you will work with leading industry tools and design/verification concepts to assist in developing the design, verification and infrastructure components of a variety of digital design blocks which are a part of the Graphics Core IP (GFXIP) at AMD. You will work closely with senior design and verification engineers to help develop a testplan for pre-silicon Digital Design Verification, assist in the development of a testbench to exercise the design, develop test-cases based on the testplan and coverpoints/assertions to achieve verification closure. You will also manage, and monitor regression runs for different blocks, report bugs/failures that occur, and actively debug the failures found.
THE PERSON:
The ideal candidate will have a strong interest in Computer Architecture, Digital Logic Design and Verification and should strive to continuously learn on the job. Excellent communication, organization and teamwork skills are paramount, as is the ability to identify and tackle different problems with diligence, whether it is a tool, flow or process issue, or a logic design and verification issue. You should be able strike a balance between collaborative problem-solving and independent solution development.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, and other DV engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Develop directed and random verification tests
- Debug test failures to determine the root cause; work with RTL design engineers to resolve design defects and correct any test issues
- Develop functional coverage properties as needed
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE:
- Solid fundamental understanding of Computer Architecture and Digital Design concepts
- Proficient in IP level ASIC verification
- Proficient in debugging DV and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux environments
- Experienced with Verilog, System Verilog, C, and C++
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment, e.g. scripting
- Exposure to simulation profile, efficiency improvement, acceleration
- Excellent understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Graphics pipeline knowledge is an asset
- Exposure to leadership or mentorship is an asset
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer Engineering/Electrical Engineering or Engineering Science or similar
This role is not eligible for visa sponsorship.
#LI-EV1
#LI-HYBRID