Radeon Technology Group (RTG) Physical Design Engineering Co-op
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
As a Co-op student, you can make an immediate contribution to AMD's next generation of technology innovations. We have a dynamic, high-energy work environment, filled with expert employees, and unique opportunities for developing your career. You will have the opportunity to connect with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. With AMD, you can get hands-on experience that will give you a competitive edge in the workforce.
Location: Markham, Ontario
We are hiring for multiple co-op/intern positions that vary between on-site and hybrid. Students will be required to work in the office on a schedule based on the team’s requirements.
Program Term: 12-month position from May 6, 2024 – April 25, 2025
The Physical Design team of the GPU Technologies and Engineering Group is responsible for the physical layout of next generation MI SoCs in the most advanced fabrication nodes. The team collaborates with IP teams and other AMD functions across the globe to assemble the SoC design and ensure that it will be sent for fabrication at spec and on schedule. The designs are executed hierarchically to accommodate the large design sizes and provide reasonable turn-around time in all stages of the design flow.
The Role
The Physical Design team accepts a gate level (or RTL in some cases) netlist, and is responsible for following tasks:
- Floorplanning – Chip sizing; block sizing; IP placement; pad placement
- Power Distribution – Create power grid for digital logic; analog power routing
- Clock Distribution – Clock trees and clock mesh for all clocks
- Block Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Chip Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Timing Closure – Static Timing Analysis of all clock domains
- EM/IR Analysis – Verification of power distribution for electro-migration and IR performance
- Physical Verification – Ensure that all design rules are met for correct and high-yield fabrication; LVS
- Tape-out – Shipment to foundry for fabrication
What you’ll be doing
- To effectively work within a team of other Physical Design Engineers and be responsible for the Physical Design for a portion of one of our ASIC’s.
- Tasks to include Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
- PD Flow development and scripting.
- Technical problem solving.
What you’ll learn
- Floorplanning – Chip sizing; block sizing; IP placement; pad placement
- Power Distribution – Create power grid for digital logic; analog power routing
- Clock Distribution – Clock trees and clock mesh for all clocks
- Block Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Chip Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Timing Closure – Static Timing Analysis of all clock domains
- EM/IR Analysis – Verification of power distribution for electro-migration and IR performance
- Physical Verification – Ensure that all design rules are met for correct and high-yield fabrication; LVS
- Tape-out – Shipment to foundry for fabrication
Key Qualifications
- 3rd year student pursuing a bachelor’s degree in Computer Engineering, Electrical Engineering, Mechatronics, Engineer Science or a related field/discipline
- Returning to school following the co-op term
Preferred Qualifications
Strong semi-conductor device physics knowledge.
- Transistor and/or logic circuit design knowledge.
- Programming experience (C++/C/Perl/Python/Verilog/UNIX scripting).
- Excellent analytical and problem-solving skills along with attention to details.
By submitting your application, you are indicating your interest in AMD co-op positions. We are recruiting for multiple positions, and if your experience aligns with any of our co-op opportunities, a recruiter will contact you.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
As a Co-op student, you can make an immediate contribution to AMD's next generation of technology innovations. We have a dynamic, high-energy work environment, filled with expert employees, and unique opportunities for developing your career. You will have the opportunity to connect with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. With AMD, you can get hands-on experience that will give you a competitive edge in the workforce.
Location: Markham, Ontario
We are hiring for multiple co-op/intern positions that vary between on-site and hybrid. Students will be required to work in the office on a schedule based on the team’s requirements.
Program Term: 12-month position from May 6, 2024 – April 25, 2025
The Physical Design team of the GPU Technologies and Engineering Group is responsible for the physical layout of next generation MI SoCs in the most advanced fabrication nodes. The team collaborates with IP teams and other AMD functions across the globe to assemble the SoC design and ensure that it will be sent for fabrication at spec and on schedule. The designs are executed hierarchically to accommodate the large design sizes and provide reasonable turn-around time in all stages of the design flow.
The Role
The Physical Design team accepts a gate level (or RTL in some cases) netlist, and is responsible for following tasks:
- Floorplanning – Chip sizing; block sizing; IP placement; pad placement
- Power Distribution – Create power grid for digital logic; analog power routing
- Clock Distribution – Clock trees and clock mesh for all clocks
- Block Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Chip Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Timing Closure – Static Timing Analysis of all clock domains
- EM/IR Analysis – Verification of power distribution for electro-migration and IR performance
- Physical Verification – Ensure that all design rules are met for correct and high-yield fabrication; LVS
- Tape-out – Shipment to foundry for fabrication
What you’ll be doing
- To effectively work within a team of other Physical Design Engineers and be responsible for the Physical Design for a portion of one of our ASIC’s.
- Tasks to include Chip Level Floor planning, Bus / Pin Planning, Clock Tree Synthesis, Placement, Optimization, Routing, Parasitic Extraction, Static Timing Analysis, IR drop analysis, Physical Verification and Sign Off.
- PD Flow development and scripting.
- Technical problem solving.
What you’ll learn
- Floorplanning – Chip sizing; block sizing; IP placement; pad placement
- Power Distribution – Create power grid for digital logic; analog power routing
- Clock Distribution – Clock trees and clock mesh for all clocks
- Block Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Chip Place & Route – Gate level netlist to fully routed layout using industry standard tools
- Timing Closure – Static Timing Analysis of all clock domains
- EM/IR Analysis – Verification of power distribution for electro-migration and IR performance
- Physical Verification – Ensure that all design rules are met for correct and high-yield fabrication; LVS
- Tape-out – Shipment to foundry for fabrication
Key Qualifications
- 3rd year student pursuing a bachelor’s degree in Computer Engineering, Electrical Engineering, Mechatronics, Engineer Science or a related field/discipline
- Returning to school following the co-op term
Preferred Qualifications
Strong semi-conductor device physics knowledge.
- Transistor and/or logic circuit design knowledge.
- Programming experience (C++/C/Perl/Python/Verilog/UNIX scripting).
- Excellent analytical and problem-solving skills along with attention to details.
By submitting your application, you are indicating your interest in AMD co-op positions. We are recruiting for multiple positions, and if your experience aligns with any of our co-op opportunities, a recruiter will contact you.