RTL Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
We are seeking a seasoned logic designer with expertise or significant interest in IP design and development. You have had significant success driving micro-architecture, IP requirements, and development. You are meticulous about Power, Performance and Area while driving schedule and quality. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features.
THE PERSON:
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
- Define IP features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications to meet those requirements, and provide technical direction to execution teams
- Participate in the development of Architecture and Micro-architecture specifications for the Logic components.
- Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve requirements
- Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting DDR and LPDDR DRAM Technologies
- Deliver Designs that meet functional and performance requirements,
- Deliver Design that meet physical/structural design constraints (timing, area, power)
- Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bringup to coverage closure
- Work closely with SOC teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
- Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
- Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: Memory sub-system, Fabrics, Encryption, Compression, Security
- Experience analyzing memory sub-system micro-architectural features to identify performance bottlenecks within different workloads and optimize power, performance, and area
- Strong desire to deliver high quality bug free designs all the way through the silicon development process
- Strong experience in Logic design implementation using hardware description language (RTL) with BSEE/MSEE
- Strong RTL analysis skills including Verilog or system Verilog, Timing Analysis and understanding of standard cell libraries
- Hands on experience in taping out cutting edge SOC including Post-Silicon Debug experience
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
- Usage/execution of logic simulation, synthesis and familiarity with logic development flows
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- Excellent analytical and problem solving skills along with attention to details
- Excellent communication, management, and presentation skills.
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree in related discipline preferred
LOCATION: Santa Clara, Austin
#LI-TB2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
We are seeking a seasoned logic designer with expertise or significant interest in IP design and development. You have had significant success driving micro-architecture, IP requirements, and development. You are meticulous about Power, Performance and Area while driving schedule and quality. We are looking for an experienced, conscientious logic design engineer in the Dram Controller IP at AMD's Santa Clara Design Center. You will be working in a fast-paced, complex environment where you will be challenged to provide elegant, robust solutions for increasingly complex features.
THE PERSON:
You have excellent communication and presentation skills, demonstrated through technical publications, presentations, trainings, executive briefings, etc. You are highly adept at collaboration among top-thinkers and engineers alike, ready to mentor and guide, and help to elevate the knowledge and skills of the team around you.
KEY RESPONSIBILITIES:
- Define IP features and capabilities, close architecture, and micro-architecture requirements, drive technical specifications to meet those requirements, and provide technical direction to execution teams
- Participate in the development of Architecture and Micro-architecture specifications for the Logic components.
- Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve requirements
- Perform logic design, Register Transfer Level (RTL) coding for new features within existing blocks and design new blocks supporting DDR and LPDDR DRAM Technologies
- Deliver Designs that meet functional and performance requirements,
- Deliver Design that meet physical/structural design constraints (timing, area, power)
- Work with Verification Engineers to effectively communicate and resolve issues from test plan through feature bringup to coverage closure
- Work closely with SOC teams for Area and Floorplan refinement, Verification Test plan reviews, Timing targets, Emulation plans, Pre-Si bug resolution and Performance/Power Verification sign offs
- Support Post-Si teams for Product Performance, Power and functional issues debug/resolution
PREFERRED EXPERIENCE:
- Outstanding foundation in Systems & SoC architecture, with expertise in one or more of the following: Memory sub-system, Fabrics, Encryption, Compression, Security
- Experience analyzing memory sub-system micro-architectural features to identify performance bottlenecks within different workloads and optimize power, performance, and area
- Strong desire to deliver high quality bug free designs all the way through the silicon development process
- Strong experience in Logic design implementation using hardware description language (RTL) with BSEE/MSEE
- Strong RTL analysis skills including Verilog or system Verilog, Timing Analysis and understanding of standard cell libraries
- Hands on experience in taping out cutting edge SOC including Post-Silicon Debug experience
- Working experience on CAD tools from Synopsys, Cadence and Mentor Graphics
- Usage/execution of logic simulation, synthesis and familiarity with logic development flows
- Must be a self-starter, and be able to independently and efficiently drive tasks to completion
- Excellent analytical and problem solving skills along with attention to details
- Excellent communication, management, and presentation skills.
- Adept at collaboration among top-thinkers and senior architects with strong interpersonal skills to work across teams in different geographies
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s degree in related discipline preferred
LOCATION: Santa Clara, Austin
#LI-TB2