Senior Staff Silicon Design Engineer (IOHub)
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Data Center GPU, Server, Client, Embedded and Semi-Custom. NBIO global operates seamless from China, North America, India and Europe.
IOHUB sits in the center of all data paths, it includes 2 foundation IP (name as IOHub Core and IOMMU) and one IOHUB Subsystem. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection, it plays a critical role on IO virtualization technology which is widely used in mega-data center.
We are searching for a lead for IOHUB Subsystem verification and Project execution.
THE PERSON:
People who have the passion to work on leading edge technology, who have solid verification capability and communication skills will be successful in this role.
- Strong team spirit
- Drive to completion
- Fluent verbal English and good communication
KEY RESPONSIBILITIES:
- IOHUB Subsystem verification strategy and scoping
- IOHUB Subsystem test plan, DRVR implementation and verification closure
- Closely work with Design/Architecture team to develop new verification components
- Organize/attend conference call for strategy alignment, status sync up etc. with global team
- Short term global travel if needed
PREFERRED EXPERIENCE:
- Global company working experience background, fluent oral English
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
- Good knowledge of UVM/Verilog/System C/System Verilog.
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
- Experience of execution lead is an asset.
- Knowledge of Virtualization is an asset.
- Scripting languages (Perl, C Shell, Makefile, …) experience.
ACADEMIC CREDENTIALS:
- MSEE within 8+ years, or BSEE within 10+ years’ experience in digital ASIC/SOC design verification.
LOCATION:
Penang
#LI-FY
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
AMD NBIO (North Bridge IO) team delivers industry leading high-performance interconnects IP for all AMD products including dGPU, Data Center GPU, Server, Client, Embedded and Semi-Custom. NBIO global operates seamless from China, North America, India and Europe.
IOHUB sits in the center of all data paths, it includes 2 foundation IP (name as IOHub Core and IOMMU) and one IOHUB Subsystem. IOhub Core is the PCI “host bridge” of the system which provides decoding and routing services to PCIe etc. devices. IOMMU (I/O Memory Management Unit) is responsible for address translation and memory protection, it plays a critical role on IO virtualization technology which is widely used in mega-data center.
We are searching for a lead for IOHUB Subsystem verification and Project execution.
THE PERSON:
People who have the passion to work on leading edge technology, who have solid verification capability and communication skills will be successful in this role.
- Strong team spirit
- Drive to completion
- Fluent verbal English and good communication
KEY RESPONSIBILITIES:
- IOHUB Subsystem verification strategy and scoping
- IOHUB Subsystem test plan, DRVR implementation and verification closure
- Closely work with Design/Architecture team to develop new verification components
- Organize/attend conference call for strategy alignment, status sync up etc. with global team
- Short term global travel if needed
PREFERRED EXPERIENCE:
- Global company working experience background, fluent oral English
- Complex IP/ASIC/SOC Design Verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCI-e, HT) is preferred.
- Good knowledge of UVM/Verilog/System C/System Verilog.
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA), insights into random techniques.
- Experience of execution lead is an asset.
- Knowledge of Virtualization is an asset.
- Scripting languages (Perl, C Shell, Makefile, …) experience.
ACADEMIC CREDENTIALS:
- MSEE within 8+ years, or BSEE within 10+ years’ experience in digital ASIC/SOC design verification.
LOCATION:
Penang
#LI-FY
#LI-Hybrid