Silicon Design Engineer 2
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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SILICON DESIGN ENGINEER 2
THE ROLE:
As a Silicon Design Engineer, you will work with design verification experts and designers to verify next generation SOC design and drive convergence.
The SOC Design Verification team verifies hardware design using software languages such as C++, System Verilog and UVM. We ensure critical design features such as clock, bootup, network data paths work as expected before chip fabrication. This role involves developing knowledge in how design blocks interact in a System-On-Chip environment, the various data flows in a SOC environment, an understanding of design features, how tests are written and regressed, and optimizing verification methodology. We optimize our verification solutions to enhance simulation performance and test modularity using various programming and scripting languages. The culture and team dynamic are one of the key attributes of the SOC Design Verification team.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Build directed and random verification tests, sequences, and testbench components in C++, SystemVerilog and UVM along with formal to achieve verification of the design
- Responsible for verification quality metrics like pass rates, code coverage and functional coverage
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
PREFERRED EXPERIENCE:
- Project level experience with design concepts and RTL implementation for same
- Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
- Good understanding of computer organization/architecture
- Experienced with debugging firmware and RTL code using simulation tools
- Experienced with using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Scripting language experience: Perl, Ruby, Makefile, shell preferred
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer engineering/Electrical Engineering, Computer Science with Hardware Courses
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Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SILICON DESIGN ENGINEER 2
THE ROLE:
As a Silicon Design Engineer, you will work with design verification experts and designers to verify next generation SOC design and drive convergence.
The SOC Design Verification team verifies hardware design using software languages such as C++, System Verilog and UVM. We ensure critical design features such as clock, bootup, network data paths work as expected before chip fabrication. This role involves developing knowledge in how design blocks interact in a System-On-Chip environment, the various data flows in a SOC environment, an understanding of design features, how tests are written and regressed, and optimizing verification methodology. We optimize our verification solutions to enhance simulation performance and test modularity using various programming and scripting languages. The culture and team dynamic are one of the key attributes of the SOC Design Verification team.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team player who has excellent communication skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Build directed and random verification tests, sequences, and testbench components in C++, SystemVerilog and UVM along with formal to achieve verification of the design
- Responsible for verification quality metrics like pass rates, code coverage and functional coverage
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
PREFERRED EXPERIENCE:
- Project level experience with design concepts and RTL implementation for same
- Experience or familiarity with formal tools and/or functional verification tools by VCS, Cadence, Mentor Graphics
- Good understanding of computer organization/architecture
- Experienced with debugging firmware and RTL code using simulation tools
- Experienced with using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Scripting language experience: Perl, Ruby, Makefile, shell preferred
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in Computer engineering/Electrical Engineering, Computer Science with Hardware Courses
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