SMTS Hardware Development Eng.
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
This person will be part of next generation Design Verification team. Requires strong hands-on knowledge of all facets of the SOC design verificaiton process and strong knowledge of IP/SOC Architecture.
THE PERSON:
A successful candidate will work with SoC Arch team, participate in design feature reviews and verification scoping. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Must have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:
- Strong knowledge in IP/SOC design methodologies.
- Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
- Mentoring juniors and enhancing their skill set
- Must have strong knowledge of AMBA AHB/AXI protocol
- Working knowledge on code coverage, functional coverage, Lint, CDC etc
- IP development and coding using standard coding guide lines knowledge
- Excellent communication skills. Must be able to participate & lead in global meetings
- Soft skills to be able to work in a cross functional international team digital and software design engineers
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme
PREFERRED EXPERIENCE:
- 10+ Years for experience
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
#LI-PK2
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
This person will be part of next generation Design Verification team. Requires strong hands-on knowledge of all facets of the SOC design verificaiton process and strong knowledge of IP/SOC Architecture.
THE PERSON:
A successful candidate will work with SoC Arch team, participate in design feature reviews and verification scoping. The candidate will be highly accurate and detail-oriented, possessing good communication and problem-solving skills. Must have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBLITIES:
- Strong knowledge in IP/SOC design methodologies.
- Sound knowledge of RTL/SOC design/integration with Verilog/system Verilog
- Mentoring juniors and enhancing their skill set
- Must have strong knowledge of AMBA AHB/AXI protocol
- Working knowledge on code coverage, functional coverage, Lint, CDC etc
- IP development and coding using standard coding guide lines knowledge
- Excellent communication skills. Must be able to participate & lead in global meetings
- Soft skills to be able to work in a cross functional international team digital and software design engineers
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified
- Build test plan documentation, accounting for interactions with other features, the hardware, the firmware, and the software driver use cases
- Estimate the time required to write the new feature tests and any required changes to the test environment
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and firmware engineers to resolve design defects and correct any test issues
- Review functional and code coverage metrics - modify or add tests or constrain random tests to meet the coverage requireme
PREFERRED EXPERIENCE:
- 10+ Years for experience
- Proficient in IP level ASIC verification
- Proficient in debugging firmware and RTL code using simulation tools
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Developing UVM based verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment.
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux with exposure to Windows platform
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Good working knowledge of SystemC and TLM with some related experience.
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Desirable assets with prior exposure to video codec system or other multimedia solutions.
#LI-PK2