SMTS Silicon Design Engineer (Low power Verification Lead )
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SMTS SILICON DESIGN ENGINEER
THE ROLE (Low power Verification Lead):
As a member of the S3 Group, you will help bring to life cutting-edge designs. As a member of the front-end design Verification team, you will work closely work with the architecture, IP design/Verif , SOC Design, Physical Design teams, and product engineers to achieve first pass silicon success. This role is very specifically focused on the low power verification where the power aware verification is done for the complex SOC's which has multi power domains. As a Power management DV lead, priority task is on problem solving by being one among the team and provide adequate guidance on the technical issues occurs during SOC verification. If you have the working experience with CPF/UPF flow/expert in system verilog/uVM and C++ based test bench development/expert in SOC debug/very good knowledge in processor architecture and Control and data flow in SOC; then you might be the right candidate for this position.
THE PERSON:
- Leader with strong self-driving ability
- Need excellent communication skills (both written and oral)
- Strong problem-solving skills, go to person for IP deployment/integration activities.
KEY RESPONSIBILITIES:
- Verification of Low power architecture and low power features in SOC
- Test bench development and test case development using SV/uVM and C++ with power aware verification support.
- Drive the team for the bug free silicon deliverable and increase the efficiency by adapting the possible automation in the environment.
- Will work with various IP & SOC teams across the globe (GFX, Memory controller, Multimedia engines, IOs, PCIe etc.) to understand the features and create verification plans
- Will help scoping out the testbench architecture and the simulation configuration.
- Will develop all the power sequences to various power states at the SOC
- Manage the callouts to Ips and verify the SOC context for IP level low power features.
- Will work on creating test bench components like checkers, monitors, test cases, coverage infrastructure, running simulations, debug, coverage analysis & closure etc.
- This person will work on low power verification using VCLP/NLP, verification with ULPs and gatesims etc.
- Identify the key tools, evaluate the same and integrate, if found to be useful for the team.
- Drive the connectivity checks as part of integration, have the associated assertions to have the SOC integration checks and drive for the automation to have all required methodologies in place.
- Running regular execution meetings and scrums to resolve bottlenecks with team.
- Project planning including schedule, deliverables, risk identification and mitigations options.
- Drive the team for the bug free silicon deliverable and increase the efficiency by adapting the possible automation in the environment.
PREFERRED EXPERIENCE:
- Experience with SOC verification that involves x86 core, Graphics core, memory subsystem, PCIE subsystems, cache coherency, interconnects etc.
- Experience with setting up verification infrastructure would be desirable.
- Experience with verification of SOC power management and handling of different power states.
- Should have strong experience with SV/UVM Methodology along with C based or mix language test cases.
- Must have excellent knowledge of Design & verification flows
- Experience in writing test plans and test cases
- Excellent hands-on debug skills
- Strong Verilog, UVM, System Verilog, PLI/DPI interface, SystemC or C/C++, Perl/shell script programming skills.
- Must have good communication skills and the ability and desire to foster a team environment.
- Must be well organized and should be good at multi-tasking.
- Should be a confident coder and be comfortable debugging general hardware/software problems.
- Work with a team of Architects, Hardware and Software engineers to Define the product use case scenarios.
- Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.
- Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.
- Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks identification and mitigation plan.
- JIRA based project management is a plus.
ACADEMIC CREDENTIALS:
- BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE
- ~12-16 years of strong DV experience in IP, Sub System & SOC Verification, IP deployment/integration.
#LI-SR4
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
THE ROLE (Low power Verification Lead):
As a member of the S3 Group, you will help bring to life cutting-edge designs. As a member of the front-end design Verification team, you will work closely work with the architecture, IP design/Verif , SOC Design, Physical Design teams, and product engineers to achieve first pass silicon success. This role is very specifically focused on the low power verification where the power aware verification is done for the complex SOC's which has multi power domains. As a Power management DV lead, priority task is on problem solving by being one among the team and provide adequate guidance on the technical issues occurs during SOC verification. If you have the working experience with CPF/UPF flow/expert in system verilog/uVM and C++ based test bench development/expert in SOC debug/very good knowledge in processor architecture and Control and data flow in SOC; then you might be the right candidate for this position.
THE PERSON:
- Leader with strong self-driving ability
- Need excellent communication skills (both written and oral)
- Strong problem-solving skills, go to person for IP deployment/integration activities.
KEY RESPONSIBILITIES:
- Verification of Low power architecture and low power features in SOC
- Test bench development and test case development using SV/uVM and C++ with power aware verification support.
- Drive the team for the bug free silicon deliverable and increase the efficiency by adapting the possible automation in the environment.
- Will work with various IP & SOC teams across the globe (GFX, Memory controller, Multimedia engines, IOs, PCIe etc.) to understand the features and create verification plans
- Will help scoping out the testbench architecture and the simulation configuration.
- Will develop all the power sequences to various power states at the SOC
- Manage the callouts to Ips and verify the SOC context for IP level low power features.
- Will work on creating test bench components like checkers, monitors, test cases, coverage infrastructure, running simulations, debug, coverage analysis & closure etc.
- This person will work on low power verification using VCLP/NLP, verification with ULPs and gatesims etc.
- Identify the key tools, evaluate the same and integrate, if found to be useful for the team.
- Drive the connectivity checks as part of integration, have the associated assertions to have the SOC integration checks and drive for the automation to have all required methodologies in place.
- Running regular execution meetings and scrums to resolve bottlenecks with team.
- Project planning including schedule, deliverables, risk identification and mitigations options.
- Drive the team for the bug free silicon deliverable and increase the efficiency by adapting the possible automation in the environment.
PREFERRED EXPERIENCE:
- Experience with SOC verification that involves x86 core, Graphics core, memory subsystem, PCIE subsystems, cache coherency, interconnects etc.
- Experience with setting up verification infrastructure would be desirable.
- Experience with verification of SOC power management and handling of different power states.
- Should have strong experience with SV/UVM Methodology along with C based or mix language test cases.
- Must have excellent knowledge of Design & verification flows
- Experience in writing test plans and test cases
- Excellent hands-on debug skills
- Strong Verilog, UVM, System Verilog, PLI/DPI interface, SystemC or C/C++, Perl/shell script programming skills.
- Must have good communication skills and the ability and desire to foster a team environment.
- Must be well organized and should be good at multi-tasking.
- Should be a confident coder and be comfortable debugging general hardware/software problems.
- Work with a team of Architects, Hardware and Software engineers to Define the product use case scenarios.
- Comfortable with design/verification tools and flows like VCS, Verdi, SOC Connectivity, SV assertions, HW-SW co-simulations, UPF/CPF flows etc.
- Strong understanding of System integration, Make file flow, Verification Methodologies, Boot up sequence.
- Expertise in managing execution team, project planning, IP delivery timelines, deliverables and quality checks, Resource planning, critical path analysis, risks identification and mitigation plan.
- JIRA based project management is a plus.
ACADEMIC CREDENTIALS:
- BE/B.Tech/ME/MTECH/MS or equivalent in ECE/EEE/CSE
- ~12-16 years of strong DV experience in IP, Sub System & SOC Verification, IP deployment/integration.
#LI-SR4