SMTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
SMTS SILICON DESIGN ENGINEER
The Graphics Memory Hub (GMHUB) team is looking for an individual to participate in the verification of key GMHUB IP components delivered to AMD’s award winning APUs and dGPUs. He/she will demonstrate enthusiasm toward design verification, be a team player, a problem solver with independence, creativity and organizational skills.
The Graphics Memory Hub (GMHUB) is an IP that delivers into many SOCs that are shipped by AMD. We deliver console, discrete graphics, and low power SoC’s and use the same testbench to verify all of our IP. There are many challenges as we refine our new testbench and take on the next generation GMHUB architecture changes and challenges. This position will enhance or develop skills sets in all of the following: Verification methodology, OVM/UVM, Random Constrained Stimulus, Coverage Driven Verification and more
KEY RESPONSIBILITIES
- Work in a team of design verification and design engineers, involved in all aspects of the verification flow from initial test planning to coverage and signoff closure under aggressive, market-driven schedules
- Build testbench components such as test libraries, models, monitors, scoreboards, sequencers, sequences, and BFMs by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++
- Drive closure of regression signatures using waveform viewer and output files; and collaborate with RTL designers to fix bugs
SKILLS AND EXPERIENCE REQUIREMENTS
- Requires demonstrated technical expertise in functional verification of complex designs including: test planning, IP test bench development, stimulus generation, checking, and functional coverage
- Significant experience with Verilog, System Verilog, and C/C++ Programming expertise are a requirement
- Working knowledge of cache structures and virtual memory management is an assert
- Experience with UVM and Perl is highly recommended - Requires strong Programming and debug skills.
- Requires strong communication skills and the ability to work independently as well as in a cross-site team environment. .
EDUCATIONAL REQUIREMENTS
- Required: Bachelor's, Computer Engineering and/or Electrical Engineering
#LI-PU1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SMTS SILICON DESIGN ENGINEER
The Graphics Memory Hub (GMHUB) team is looking for an individual to participate in the verification of key GMHUB IP components delivered to AMD’s award winning APUs and dGPUs. He/she will demonstrate enthusiasm toward design verification, be a team player, a problem solver with independence, creativity and organizational skills.
The Graphics Memory Hub (GMHUB) is an IP that delivers into many SOCs that are shipped by AMD. We deliver console, discrete graphics, and low power SoC’s and use the same testbench to verify all of our IP. There are many challenges as we refine our new testbench and take on the next generation GMHUB architecture changes and challenges. This position will enhance or develop skills sets in all of the following: Verification methodology, OVM/UVM, Random Constrained Stimulus, Coverage Driven Verification and more
KEY RESPONSIBILITIES
- Work in a team of design verification and design engineers, involved in all aspects of the verification flow from initial test planning to coverage and signoff closure under aggressive, market-driven schedules
- Build testbench components such as test libraries, models, monitors, scoreboards, sequencers, sequences, and BFMs by applying objected oriented design techniques and using advanced verification languages such as System Verilog, UVM and C++
- Drive closure of regression signatures using waveform viewer and output files; and collaborate with RTL designers to fix bugs
SKILLS AND EXPERIENCE REQUIREMENTS
- Requires demonstrated technical expertise in functional verification of complex designs including: test planning, IP test bench development, stimulus generation, checking, and functional coverage
- Significant experience with Verilog, System Verilog, and C/C++ Programming expertise are a requirement
- Working knowledge of cache structures and virtual memory management is an assert
- Experience with UVM and Perl is highly recommended - Requires strong Programming and debug skills.
- Requires strong communication skills and the ability to work independently as well as in a cross-site team environment. .
EDUCATIONAL REQUIREMENTS
- Required: Bachelor's, Computer Engineering and/or Electrical Engineering
#LI-PU1