SMTS Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
AMD NBIO DACC (Data Accelerator) team delivers industry leading high-performance DMA engine for AMD Data Center CPU and GPU. DACC is HW implementation of a new DMA engine technology co-developed with AMD’s ecosystem partners incorporating virtualization and shared virtual memory capabilities, as well as incorporating additional accelerations functions (CRC, Crypto etc). DACC is a critical ingredient of AMD’s I/O accelerator technology to service today’s Mega Data Center ever increasing computing demand. You will work with world class global team on DACC development and verification, provide technical support to various global SOC teams.
THE PERSON:
As DACC Frontend IP verification lead, responsible for participating on verification strategy definition, verification environment setup, test plan creation, lead verification execution and verification quality sign off.
KEY RESPONSIBILITIES:
- Work with hardware architects on verification strategy setup
- Work with firmware architects on interoperability test between hardware and firmware
- Lead several team members to sign off DACC IP regression/coverage to make product time to market on time
- Collaborate with global team on implementation of multiple function domains like Firmware, Formal, Power, Performance verification.
- Build re-usable components and infrastructure that can be re-used for upper-level verification env such as Subsystem, SOC
- Be involved technically system features discussion and share productive ideas from System level perspective for DACC verification strategy.
- Develop test sequence for DACC features.
- DACC DV/Deployment flow implementation
- Coaches and mentor junior staff
PREFERRED EXPERIENCE:
- Expereince on Firmware-Hardware co-simuliation
- Complex IP/ASIC/SOC design verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCIe, USB, DDR, DisplayPort)
- Solid background with ASIC design verification flow and multiple ASIC tape-out experience
- Solid knowledge on System Verilog, C/C++, Verilog
- Solid knowledge on scripting language like Perl, python, ruby
- Solid knowledge on UVM/OVM
- Experience on leading people to complete the whole verification flow
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
- Knowledge on High-speed IO/PCIE is a big plus
- Knowledge on IO Virtualization is big plus
- Fluent verbal English for technical discussion with global team
ACADEMIC CREDENTIALS:
Candidate is preferred to be MSEE with minimum of 5 years, or BSEE with minimum of 7-year experience in digital ASIC/SOC design verification.
#LI-JG2 #LI-HYBRID
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
AMD NBIO DACC (Data Accelerator) team delivers industry leading high-performance DMA engine for AMD Data Center CPU and GPU. DACC is HW implementation of a new DMA engine technology co-developed with AMD’s ecosystem partners incorporating virtualization and shared virtual memory capabilities, as well as incorporating additional accelerations functions (CRC, Crypto etc). DACC is a critical ingredient of AMD’s I/O accelerator technology to service today’s Mega Data Center ever increasing computing demand. You will work with world class global team on DACC development and verification, provide technical support to various global SOC teams.
THE PERSON:
As DACC Frontend IP verification lead, responsible for participating on verification strategy definition, verification environment setup, test plan creation, lead verification execution and verification quality sign off.
KEY RESPONSIBILITIES:
- Work with hardware architects on verification strategy setup
- Work with firmware architects on interoperability test between hardware and firmware
- Lead several team members to sign off DACC IP regression/coverage to make product time to market on time
- Collaborate with global team on implementation of multiple function domains like Firmware, Formal, Power, Performance verification.
- Build re-usable components and infrastructure that can be re-used for upper-level verification env such as Subsystem, SOC
- Be involved technically system features discussion and share productive ideas from System level perspective for DACC verification strategy.
- Develop test sequence for DACC features.
- DACC DV/Deployment flow implementation
- Coaches and mentor junior staff
PREFERRED EXPERIENCE:
- Expereince on Firmware-Hardware co-simuliation
- Complex IP/ASIC/SOC design verification, direct experience in IP/SOC or Processor (CPU or GPU) or Industry bus standard (PCIe, USB, DDR, DisplayPort)
- Solid background with ASIC design verification flow and multiple ASIC tape-out experience
- Solid knowledge on System Verilog, C/C++, Verilog
- Solid knowledge on scripting language like Perl, python, ruby
- Solid knowledge on UVM/OVM
- Experience on leading people to complete the whole verification flow
- Solid background with hardware verification methodologies such as coverage-based verification methodology with the use of hardware assertions (PSL or SVA)
- Knowledge on High-speed IO/PCIE is a big plus
- Knowledge on IO Virtualization is big plus
- Fluent verbal English for technical discussion with global team
ACADEMIC CREDENTIALS:
Candidate is preferred to be MSEE with minimum of 5 years, or BSEE with minimum of 7-year experience in digital ASIC/SOC design verification.
#LI-JG2 #LI-HYBRID