SMTS Systems Design Engineer - Server Platform Emulation Validation
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
AMD is looking for a highly talented engineer to join our Server Platform Solution Engineering (SPSE) team as a senior member of technical staff working on server platform emulation validation for next-generation AMD EPYC systems.
As a server platform emulation validation engineer, we are shift-left testing strategist specializing in AMD EPYC system testing. The focus of this role is to plan, build, and execute the verification of new and existing features for next-generation AMD EPYC systems.
THE PERSON:
You have a passion for modern, complex server architecture verification who thrives in an environment that require creative debugging skills, drive to improve pre-silicon system validation coverage capabilities, and a passion for improving the overall shift-left strategies and goals. You are a team player who has excellent communication skills, responsible and willing to pick new skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Responsible for validation of firmware stack, BIOS, OS, DFX, debug tools on pre-silicon emulation platforms
- Responsible for developing test plans and identification of design and firmware dependencies to smooth execution of test plans
- Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
- Responsible for debugging SOC level failures and working with SOC design, firmware teams to complete feature validation
- Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
- Responsible for running emulator workloads to test new features
PREFERRED EXPERIENCE:
- Good communication skill
- Experience with FPGA and/or emulation platforms
- Experience in developing System Verilog based test content
- Experience in developing C++, Python, Perl, Ruby, Shell and TCL test content
- Experience in validating hardware features for at least 2 or more projects in a pre-silicon environment
- Experience in debugging failures using waveform viewers, log files and microcode trace dumps
- Knowledge of one or more protocols: SPI, DDR, SATA, USB, AXI, PCI, PCIe, MIPI, WLAN, I2C/I3C, CXL
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s in electrical engineering, computer engineering, or comparable disciplines.
LOCATION:
Penang, Malaysia
#LI-FY
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
AMD is looking for a highly talented engineer to join our Server Platform Solution Engineering (SPSE) team as a senior member of technical staff working on server platform emulation validation for next-generation AMD EPYC systems.
As a server platform emulation validation engineer, we are shift-left testing strategist specializing in AMD EPYC system testing. The focus of this role is to plan, build, and execute the verification of new and existing features for next-generation AMD EPYC systems.
THE PERSON:
You have a passion for modern, complex server architecture verification who thrives in an environment that require creative debugging skills, drive to improve pre-silicon system validation coverage capabilities, and a passion for improving the overall shift-left strategies and goals. You are a team player who has excellent communication skills, responsible and willing to pick new skills. You have strong analytical and problem-solving skills and are willing to learn and ready to take on problems.
KEY RESPONSIBILITIES:
- Responsible for validation of firmware stack, BIOS, OS, DFX, debug tools on pre-silicon emulation platforms
- Responsible for developing test plans and identification of design and firmware dependencies to smooth execution of test plans
- Responsible for writing directed tests to verify features in a co-simulated and emulated/FPGA hardware environment
- Responsible for debugging SOC level failures and working with SOC design, firmware teams to complete feature validation
- Responsible for writing monitors and checkers to support end-to-end firmware/hardware validation
- Responsible for running emulator workloads to test new features
PREFERRED EXPERIENCE:
- Good communication skill
- Experience with FPGA and/or emulation platforms
- Experience in developing System Verilog based test content
- Experience in developing C++, Python, Perl, Ruby, Shell and TCL test content
- Experience in validating hardware features for at least 2 or more projects in a pre-silicon environment
- Experience in debugging failures using waveform viewers, log files and microcode trace dumps
- Knowledge of one or more protocols: SPI, DDR, SATA, USB, AXI, PCI, PCIe, MIPI, WLAN, I2C/I3C, CXL
ACADEMIC CREDENTIALS:
- Bachelor’s or Master’s in electrical engineering, computer engineering, or comparable disciplines.
LOCATION:
Penang, Malaysia
#LI-FY
#LI-Hybrid