SoC DFX Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
At AMD, our mission is to build great products that accelerate next-generation computing experiences—from AI and data centers, to PCs, gaming and embedded systems. Grounded in a culture of innovation and collaboration, we believe real progress comes from bold ideas, human ingenuity and a shared passion to create something extraordinary. When you join AMD, you’ll discover the real differentiator is our culture. We push the limits of innovation to solve the world’s most important challenges—striving for execution excellence, while being direct, humble, collaborative, and inclusive of diverse perspectives. Join us as we shape the future of AI and beyond. Together, we advance your career.
THE ROLE:
As part of SOC (System-On-Chip) DFX team you will be involved in design, integration, verification & timing analysis for state-of-the-art design-for-test and design-for-debug features in complex AMD products. You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification and emulation of those features until deliveries to PEO (product engineering organization) and debug on ATE (automated test equipment)
THE PERSON:
- Must have excellent written and verbal communication skills
- Must excel in a dynamic team working environment
- Leadership and mentoring skills a definite asset
- Must be a self-starter and be able to independently drive tasks to completion
- Ability to be flexible in terms of responsibilities
KEY RESPONSIBILITIES:
The successful candidate will report to the SOC DFT (Design-For-Test) Integration & Design Verification Manager and will have the following responsibilities:
- Develop RTL and integrate internal/external RTL logic into SoC (System-On-Chip)
- Write and review verification test-plans
- Develop verification infrastructure, test-bench components and test-cases
- Drive performance verification on all DFT structures
- Generate and verify DFT structural patterns and functional patterns
- Participate in ATE bring-up and debug the DFT patterns on ATE and platform
PREFERRED EXPERIENCE:
- Scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic is a plus
- Knowledge of Verilog, C/C++ and scripting languages; experience with Perl and TCL is a plus
- Familiar with entire ASIC design flow, hands on working experience on ASIC DFT design and verification is an advantage
- Knowledge of UVM and OVM verification methodologies is an advantage
- Strong analytical/problem solving skills and pronounced attention to details.
- Experience in complex ASIC design (multi-million gates) and in DFT/DFD techniques such as JTAG/IEEE standards.
- Experience in verification of multiple PHY protocols such as PCIE, XGMI, WAFL, GDDR6, USB2/3.1 and Display port is a plus
ACADEMIC CREDENTIALS:
- BS or higher in EE & CS
LOCATION:
- Markham
#LI-PH1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
As part of SOC (System-On-Chip) DFX team you will be involved in design, integration, verification & timing analysis for state-of-the-art design-for-test and design-for-debug features in complex AMD products. You will have the opportunity to be involved in all stages of the project execution from high level definition and test plan review, through design, verification and emulation of those features until deliveries to PEO (product engineering organization) and debug on ATE (automated test equipment)
THE PERSON:
- Must have excellent written and verbal communication skills
- Must excel in a dynamic team working environment
- Leadership and mentoring skills a definite asset
- Must be a self-starter and be able to independently drive tasks to completion
- Ability to be flexible in terms of responsibilities
KEY RESPONSIBILITIES:
The successful candidate will report to the SOC DFT (Design-For-Test) Integration & Design Verification Manager and will have the following responsibilities:
- Develop RTL and integrate internal/external RTL logic into SoC (System-On-Chip)
- Write and review verification test-plans
- Develop verification infrastructure, test-bench components and test-cases
- Drive performance verification on all DFT structures
- Generate and verify DFT structural patterns and functional patterns
- Participate in ATE bring-up and debug the DFT patterns on ATE and platform
PREFERRED EXPERIENCE:
- Scan and ATPG, on-chip test pattern compression and at-speed testing using PLL, memory BIST and repair, logic BIST, power-gating, on-chip debug logic is a plus
- Knowledge of Verilog, C/C++ and scripting languages; experience with Perl and TCL is a plus
- Familiar with entire ASIC design flow, hands on working experience on ASIC DFT design and verification is an advantage
- Knowledge of UVM and OVM verification methodologies is an advantage
- Strong analytical/problem solving skills and pronounced attention to details.
- Experience in complex ASIC design (multi-million gates) and in DFT/DFD techniques such as JTAG/IEEE standards.
- Experience in verification of multiple PHY protocols such as PCIE, XGMI, WAFL, GDDR6, USB2/3.1 and Display port is a plus
ACADEMIC CREDENTIALS:
- BS or higher in EE & CS
LOCATION:
- Markham
#LI-PH1