Sr. Manager Silicon Design Engineering (Design)
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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THE ROLE:
This role is an exciting opportunity for a design manager to lead a team of highly skilled design engineers within the SouthBridge IO (SBIO) team. Provide IP technical management and leadership for the end-to-end design development flow. This includes from architecture, microarchitecture, RTL design, design metrics (performance, power, area) analysis and design for verification strategy. Collaborate with design and verification teams to ensure a predictable IP development. Lead all aspects of the design from definition of microarchitecture, design to white-box verification signoff. Plan for career development of design engineers.
THE PERSON:
- Strong analytical and problem solving skills with a pronounced attention to detail
- Strong communication, mentoring and leadership skills.
- Skilled at driving team and tasks from start to completion with superior quality
- Can work well with cross functional teams and lead global projects.
KEY RESPONSIBILITIES:
- Lead team on ASIC IP design responsibilities and alignment with SoC.
- Collaborate with architects and designers to understand the IP features.
- Lead design low power design and analysis
- Present updates and provide reports to management.
- Identify and drive improvement initiatives.
PREFERRED EXPERIENCE:
- 15+ years of ASIC/SoC/FPGA development experience with 8+ years in leading a design team
- Proficient in computer architecture and interconnects.
- Proficient in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation
- Proficient in Verilog RTL design and has experience of large digital ASIC project.
- Familiarity in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt, UFS, Ethernet) is a plus
- Strong working experience in with front-end EDA tools and flows.
- Strong working experience with Unix/Linux and scripts (tcl, perl, ruby and etc.)
- Excellent interpersonal, communication, and writing skills. Able to provide clear and logical presentations and documentation. Has an open mind and attitude. Transparent. Willing to admit and learn from mistakes.
- Works well with others in a team environment
- Automating workflows in a distributed compute environment.
- Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality.
ACADEMIC CREDENTIALS:
- BS (or higher) degree in Electrical or Computer Engineering desired
LOCATION:
Penang, Malaysia
#LI-FY
#LI-Hybrid
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
This role is an exciting opportunity for a design manager to lead a team of highly skilled design engineers within the SouthBridge IO (SBIO) team. Provide IP technical management and leadership for the end-to-end design development flow. This includes from architecture, microarchitecture, RTL design, design metrics (performance, power, area) analysis and design for verification strategy. Collaborate with design and verification teams to ensure a predictable IP development. Lead all aspects of the design from definition of microarchitecture, design to white-box verification signoff. Plan for career development of design engineers.
THE PERSON:
- Strong analytical and problem solving skills with a pronounced attention to detail
- Strong communication, mentoring and leadership skills.
- Skilled at driving team and tasks from start to completion with superior quality
- Can work well with cross functional teams and lead global projects.
KEY RESPONSIBILITIES:
- Lead team on ASIC IP design responsibilities and alignment with SoC.
- Collaborate with architects and designers to understand the IP features.
- Lead design low power design and analysis
- Present updates and provide reports to management.
- Identify and drive improvement initiatives.
PREFERRED EXPERIENCE:
- 15+ years of ASIC/SoC/FPGA development experience with 8+ years in leading a design team
- Proficient in computer architecture and interconnects.
- Proficient in full ASIC design cycle: requirements definition, architectural and micro-architectural specification, RTL, design verification, floor-planning, synthesis, timing closure, post-silicon validation
- Proficient in Verilog RTL design and has experience of large digital ASIC project.
- Familiarity in high speed IO controller design (e.g. USB, PCIe, SATA, Thunderbolt, UFS, Ethernet) is a plus
- Strong working experience in with front-end EDA tools and flows.
- Strong working experience with Unix/Linux and scripts (tcl, perl, ruby and etc.)
- Excellent interpersonal, communication, and writing skills. Able to provide clear and logical presentations and documentation. Has an open mind and attitude. Transparent. Willing to admit and learn from mistakes.
- Works well with others in a team environment
- Automating workflows in a distributed compute environment.
- Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality.
ACADEMIC CREDENTIALS:
- BS (or higher) degree in Electrical or Computer Engineering desired
LOCATION:
Penang, Malaysia
#LI-FY
#LI-Hybrid