Sr. Manager Silicon Design Engineering
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Sr. Manager, NPU Silicon Design Engineering
We are seeking an experienced RTL Design Leader/Manager with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers. It is a challenging position that involves working at a fast pace & agility to meet Quality & schedule for the IP delivery. Come join the AMD team!
THE ROLE:
We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator.
This role requires deep understanding of design implementation and flows, tools and methodologies.
THE PERSON:
The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs.
The candidate must be able to communicate effectively and work optimally with different teams across AMD. The candidate must have excellent analytical and problem-solving skills.
KEY RESPONISIBILITES:
- Manage design and front-end integration team for NPU.
- Drive the design execution using technical expertise, mentoring team of engineers & being responsible for overall execution Quality & schedule. Define and implement RTL design methodologies and best practices. Lead team, meet schedule commitments and provide strong support to various customers.
- Ensure Design meets performance, power and Area targets & verification coverage for successful silicon.
- Work with verification and physical design teams to achieve high quality design and successful tape out
- Collaborate with cross-functional team for successful and on-time delivery of NPU.
PREFERRED EXPERIENCES:
- Strong design experience in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex SOC like CPU/GPU.
- Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
- Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
- Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
- Hands-on with TCL, Perl, Python scripting,
- Strong verbal and written communication skills
#LI-NR1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Sr. Manager, NPU Silicon Design Engineering
We are seeking an experienced RTL Design Leader/Manager with strong technical and leadership skills, who thrives in a fast-paced environment, to lead a talented team of engineers. It is a challenging position that involves working at a fast pace & agility to meet Quality & schedule for the IP delivery. Come join the AMD team!
THE ROLE:
We are looking for a Senior Manager Silicon Design Engineering to lead a team of talented engineers in developing NPU IP. This IP goes to several products including client and embedded products and serves as AI inference accelerator.
This role requires deep understanding of design implementation and flows, tools and methodologies.
THE PERSON:
The ideal candidate should have demonstrated experience in leading front-end design and integration of sub-systems for complex SOCs.
The candidate must be able to communicate effectively and work optimally with different teams across AMD. The candidate must have excellent analytical and problem-solving skills.
KEY RESPONISIBILITES:
- Manage design and front-end integration team for NPU.
- Drive the design execution using technical expertise, mentoring team of engineers & being responsible for overall execution Quality & schedule. Define and implement RTL design methodologies and best practices. Lead team, meet schedule commitments and provide strong support to various customers.
- Ensure Design meets performance, power and Area targets & verification coverage for successful silicon.
- Work with verification and physical design teams to achieve high quality design and successful tape out
- Collaborate with cross-functional team for successful and on-time delivery of NPU.
PREFERRED EXPERIENCES:
- Strong design experience in ASIC designs, RTL design in Verilog/System Verilog, preferably in complex SOC like CPU/GPU.
- Modern SOC tools such as Spyglass, Questa CDC, Cadence Conformal Low Power, VCS simulation
- Experience for power domains and power islands using UPF flows and Cadence Conformal Low Power.
- Expertise in circuit timing/STA, and practical experience with Prime Time or equivalent tools
- Hands-on with TCL, Perl, Python scripting,
- Strong verbal and written communication skills
#LI-NR1