Sr. Silicon Design Engineer
Overview
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
Responsibilities
Senior Design Engineer
The Role:
We, the VCN (Video Codec Next) IP team, are based in Markham, ON, Canada. We focus on video codec IP development for AMD SOCs with leading ASIC technology. We are looking for a self-motivated, senior design engineer in the Great Toronto area to complement our team to develop world class video solutions to the highest standards.
The Person:
You are expected to actively collaborate with various team members to understand design requirements, drive block level development, IP level bring-up, timing/area/performance trade-off throughout the design cycle. Solid technical skill, self-driven attitude, and excellent communication skill especially remotely are key factors to make you successful in this organization.
Key Responsibilities:
- Draft block level design requirement, micro-architecture spec.
- Perform block level modeling, RTL/HLS implementation.
- Define block programming model and interact with firmware/software team to bring-up functionality at IP and SOC level.
- Perform design metrics checks such as LINT, CDC, synthesis, static timing analysis and power analysis.
- Work with verification engineers to define test plan and functional coverage.
- Engage verification closure, including test debug, code coverage and functional coverage review and sign-off.
- Responsible for bug fixes, including engineering change order (ECO) implementation and verification through formal verification.
Preferred Experience:
- Minimum 2 years of solid ASIC/FPGA design and verification experience.
- Rich knowledge about ASIC design flow from specification, implementation, to verification.
- Strong in SystemC, C++/C programming.
- Solid RTL design experience using Verilog.
- Experience using HLS methodology in complex design implementation and verification is a definite asset
- Familiar with CAD tools of simulation, SystemC to RTL synthesis, RTL to gate synthesis, static timing analysis and formal verification.
- Handy in Linux script languages such as Perl, Python, Ruby or/and shell languages.
- Solid problem solving skill.
- Prior team, technical leadership or mentorship are great value added asset
- Good team player and communicator
- Basic video codec knowledge is definitely a plus.
Academic Credentials:
Minimum Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering. Master degree with relevant video experience is a plus.
#LI-PU1
Qualifications
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Senior Design Engineer
The Role:
We, the VCN (Video Codec Next) IP team, are based in Markham, ON, Canada. We focus on video codec IP development for AMD SOCs with leading ASIC technology. We are looking for a self-motivated, senior design engineer in the Great Toronto area to complement our team to develop world class video solutions to the highest standards.
The Person:
You are expected to actively collaborate with various team members to understand design requirements, drive block level development, IP level bring-up, timing/area/performance trade-off throughout the design cycle. Solid technical skill, self-driven attitude, and excellent communication skill especially remotely are key factors to make you successful in this organization.
Key Responsibilities:
- Draft block level design requirement, micro-architecture spec.
- Perform block level modeling, RTL/HLS implementation.
- Define block programming model and interact with firmware/software team to bring-up functionality at IP and SOC level.
- Perform design metrics checks such as LINT, CDC, synthesis, static timing analysis and power analysis.
- Work with verification engineers to define test plan and functional coverage.
- Engage verification closure, including test debug, code coverage and functional coverage review and sign-off.
- Responsible for bug fixes, including engineering change order (ECO) implementation and verification through formal verification.
Preferred Experience:
- Minimum 2 years of solid ASIC/FPGA design and verification experience.
- Rich knowledge about ASIC design flow from specification, implementation, to verification.
- Strong in SystemC, C++/C programming.
- Solid RTL design experience using Verilog.
- Experience using HLS methodology in complex design implementation and verification is a definite asset
- Familiar with CAD tools of simulation, SystemC to RTL synthesis, RTL to gate synthesis, static timing analysis and formal verification.
- Handy in Linux script languages such as Perl, Python, Ruby or/and shell languages.
- Solid problem solving skill.
- Prior team, technical leadership or mentorship are great value added asset
- Good team player and communicator
- Basic video codec knowledge is definitely a plus.
Academic Credentials:
Minimum Bachelor of Science Degree in Electrical Engineering, Computer Science, or Computer Engineering. Master degree with relevant video experience is a plus.
#LI-PU1