Sr. Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE:
AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of being a part of the PCIe Subsystem team. In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for architecting and verifying multiple critical IPs and/or various subsystems, as well as the internal IP integration and external deployment to SoC. The team is also the pioneer on creating advanced testbenches using leading-edge verification techniques and adapting evolutionary AI/ML tools for design/verification.
THE PERSON:
A successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, quick learning, and problem-solving skills. Can work well with cross functional teams, and willing to dive into different fields to achieve the goal. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.
KEY RESPONSIBILITIES:
- Collaborate with architects and designers to understand IP features, PCIE subsystem architectures and SoC architectures.
- Setup and/or update topologies and configurations for different PCIE subsystems in difference AMD products.
- Bring up the subsystem framework for design and verification purposes in each project.
- Build, maintain and improve testbench components as well as developing test and sequence libraries, by applying OOP verification techniques following UVM methodology.
- Construct design/verification infrastructure and flow to enhance stability, reusability, compatibility, and efficiency for the team.
- Support internal IP integration for the subsystem, internal subsystem integration for other DV/EMU teams, and external subsystem deployment for the SoC.
- Evaluate and deploy new methodologies and tools for design, verification, planning and coverage.
- Technical leadership, including block ownership from start to finish and verification sign-off.
PREFERRED EXPERIENCE:
- Strong background in ASIC Design Flow.
- Good knowledge in Design Verification.
- Proficient in Verilog and System Verilog.
- Proficient in GNU Make and programming scripts such as Perl, Python, Ruby and so on.
- Familiarity with verification methodologies such as UVM, formal and so on.
- Strong analytical and problem-solving skills with pronounced attention to detail.
- Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality.
- Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB or Ethernet is a plus.
- Experience with verification of hardware-firmware interaction is a plus.
- Knowledge in performance verification is a plus.
- Knowledge in Jenkins is a plus.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: Markham, ON
#LI-RD1
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE:
AMD is looking for an experienced Design Verification Engineer willing to take on the challenge of being a part of the PCIe Subsystem team. In this role you will be given an opportunity to work on the next generation technology that will be part of future AMD Microprocessors powering Gaming Consoles, Servers and Personal Computers as well as Graphics Cards and VR sets. This team is responsible for architecting and verifying multiple critical IPs and/or various subsystems, as well as the internal IP integration and external deployment to SoC. The team is also the pioneer on creating advanced testbenches using leading-edge verification techniques and adapting evolutionary AI/ML tools for design/verification.
THE PERSON:
A successful candidate will work with architects and fellow design and verification leads. The candidate will be highly accurate and detail-oriented, possessing strong communication, quick learning, and problem-solving skills. Can work well with cross functional teams, and willing to dive into different fields to achieve the goal. Skilled at driving team and tasks from start to completion with superior quality. Drives to learn and perform at his or her highest potential in a technical capacity. Flexible in working hours to accommodate working with co-workers in different time-zones.
KEY RESPONSIBILITIES:
- Collaborate with architects and designers to understand IP features, PCIE subsystem architectures and SoC architectures.
- Setup and/or update topologies and configurations for different PCIE subsystems in difference AMD products.
- Bring up the subsystem framework for design and verification purposes in each project.
- Build, maintain and improve testbench components as well as developing test and sequence libraries, by applying OOP verification techniques following UVM methodology.
- Construct design/verification infrastructure and flow to enhance stability, reusability, compatibility, and efficiency for the team.
- Support internal IP integration for the subsystem, internal subsystem integration for other DV/EMU teams, and external subsystem deployment for the SoC.
- Evaluate and deploy new methodologies and tools for design, verification, planning and coverage.
- Technical leadership, including block ownership from start to finish and verification sign-off.
PREFERRED EXPERIENCE:
- Strong background in ASIC Design Flow.
- Good knowledge in Design Verification.
- Proficient in Verilog and System Verilog.
- Proficient in GNU Make and programming scripts such as Perl, Python, Ruby and so on.
- Familiarity with verification methodologies such as UVM, formal and so on.
- Strong analytical and problem-solving skills with pronounced attention to detail.
- Capable of independently driving tasks and activities to completion in an organized and timely manner with excellent quality.
- Familiarity with industry standard high-speed protocols such as PCIe, SATA, USB or Ethernet is a plus.
- Experience with verification of hardware-firmware interaction is a plus.
- Knowledge in performance verification is a plus.
- Knowledge in Jenkins is a plus.
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
LOCATION: Markham, ON
#LI-RD1