Sr. Silicon Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
THE ROLE
Great opportunity for a Senior Design Engineer career professional to join an elite team to develop ongoing solutions in the Adaptive & Embedded Computing Group (AECG) division of AMD semiconductor. AMD’s new hardware programmable SoC FPGAs and Adaptive Compute Acceleration Platform (ACAP) deliver most dynamic processor technology and are achieving record performances in Data Center, Wireless/5G, Automotive/ADAS and Emulation applications. These new applications, and heterogeneous computing architecture introduces new challenges in compilation, particularly in placement and routing. AMD’s Software Implementation Tools team addresses these challenges.
THE PERSON
AECG Central Engineering Network-On-Chip (NoC) Subsystem team is seeking a senior engineer to contribute to the next generation of AMD’s devices built around AMD’s Xilinx's NoC IP. And collaborate with architecture, and integration teams to create new highly integrated multi-core heterogeneous compute platform (ACAP)
KEY RESPONSIBILITIES:
- Collaborate with architecture, and integration teams to create new highly integrated multi-core heterogeneous compute platform (ACAP)
- Micro architecture and RTL design
- Write optimal timing constraints (SDC)
- Run design sanity checker tools such as LINT, CDC, FishTail, etc.
- Work closely with physical design team during implementation
- Document design and effective verbal communication
- Work verification and system validation teams to ensure design quality
- Document design and demonstrate effective verbal communication
PREFERRED EXPERIENCES:
- Over five (5) year’s workspace experience in Verilog / System Verilog (ASIC, FPGA, IP)
- Scripting in Python, Perl, TCL
ACADEMIC CREDENTIALS:
- Bachelor or Master’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or related equivalent, PhD desired but not required
LOCATION: San Jose, CA
COMPENSATION:
Expected to range from $90,440 to $167,960, commensurate with experience and specific skill sets
#LI-NM1
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
At AMD, your base pay is one part of your total rewards package. Your base pay will depend on where your skills, qualifications, experience, and location fit into the hiring range for the position. You may be eligible for incentives based upon your role such as either an annual bonus or sales incentive. Many AMD employees have the opportunity to own shares of AMD stock, as well as a discount when purchasing AMD stock if voluntarily participating in AMD’s Employee Stock Purchase Plan. You’ll also be eligible for competitive benefits described in more detail here.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
THE ROLE
Great opportunity for a Senior Design Engineer career professional to join an elite team to develop ongoing solutions in the Adaptive & Embedded Computing Group (AECG) division of AMD semiconductor. AMD’s new hardware programmable SoC FPGAs and Adaptive Compute Acceleration Platform (ACAP) deliver most dynamic processor technology and are achieving record performances in Data Center, Wireless/5G, Automotive/ADAS and Emulation applications. These new applications, and heterogeneous computing architecture introduces new challenges in compilation, particularly in placement and routing. AMD’s Software Implementation Tools team addresses these challenges.
THE PERSON
AECG Central Engineering Network-On-Chip (NoC) Subsystem team is seeking a senior engineer to contribute to the next generation of AMD’s devices built around AMD’s Xilinx's NoC IP. And collaborate with architecture, and integration teams to create new highly integrated multi-core heterogeneous compute platform (ACAP)
KEY RESPONSIBILITIES:
- Collaborate with architecture, and integration teams to create new highly integrated multi-core heterogeneous compute platform (ACAP)
- Micro architecture and RTL design
- Write optimal timing constraints (SDC)
- Run design sanity checker tools such as LINT, CDC, FishTail, etc.
- Work closely with physical design team during implementation
- Document design and effective verbal communication
- Work verification and system validation teams to ensure design quality
- Document design and demonstrate effective verbal communication
PREFERRED EXPERIENCES:
- Over five (5) year’s workspace experience in Verilog / System Verilog (ASIC, FPGA, IP)
- Scripting in Python, Perl, TCL
ACADEMIC CREDENTIALS:
- Bachelor or Master’s Degree in Computer Science, Computer Engineering, Electrical Engineering, or related equivalent, PhD desired but not required
LOCATION: San Jose, CA
COMPENSATION:
Expected to range from $90,440 to $167,960, commensurate with experience and specific skill sets
#LI-NM1