SR. STAFF DFT ENGINEER(TECH LEAD)
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SR. STAFF DFT ENGINEER( TECH LEAD)
THE ROLE:
We are seeking a highly experienced DFT engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of CPU core design and development.
As a DFT engineer in AMD's CPU Cores team, you will have an outstanding opportunity to work on AMD’s next-generation CPU core designs. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.
As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will exhibit exceptional knowledge in Design for Testability (DFT) and possess extensive experience, complemented by a robust, self-motivated work ethic and strong leadership qualities.
The ideal candidate should demonstrate a genuine passion for modern, complex processor architectures, digital design and verification, and an overall enthusiasm for DFT. As a collaborative team player, you will have outstanding communication skills and experience in working effectively with engineers across various locations and time zones. Your strong analytical and problem-solving abilities will empower you to tackle challenges enthusiastically and with a willingness to learn.
Additionally, you should have a keen eye for detail and the capability to think critically. The role requires a proactive self-starter who can take initiative and independently drive tasks to successful completion.
KEY RESPONSIBLITIES: Strong prior experience in all or at least some of the key areas below would be needed
- Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products.
- Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort.
- Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs.
- Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration.
- Work closely with DFT Tool Vendors and drive improvements based on the testability requirements.
- Develop efficient DFx flows and methodology compatible with front end and back end design flows.
- Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement.
- Mentor and coach junior engineers
PREFERRED EXPERIENCE: Strong prior experience in all or at least some of the key areas below would be preferred
- Prior work experience in high-performance and low-power designs would be a huge bonus.
- Understanding of low-power design flows such as power/clock gating, multi-Vt and voltage/frequency scaling etc will be a plus.
- Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
- Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills are critical
- Strong experience in Scan based testing and industry standard ATPG CAD tools desired.
- Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc.
- Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools.
- Experience in MBIST implementation and verification will be a strong plus.
- Good understanding of STA concepts having handled DFT timing closure before would be a plus.
- Experience in Spyglass based DFT DRC checks at RTL level would be a plus.
- Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus.
- Prior experience in working with Version control systems like perforce, git etc would be critical.
- Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks would be a plus.
- Familiarity with System Verilog and UVM would be a plus.
- Exposure to post-silicon testing and tester pattern debug are major assets.
- Strong problem solving and debug skills across various levels of design hierarchies.
- Must have good communication skills and the ability to work in a worldwide team environment.
ACADEMIC CREDENTIALS:
- Bachelors or Masters or PhD in Computer engineering/Electrical engineering/Electronics Engineering
#LI-PL1
#LI-Hybrid
#CORE
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
SR. STAFF DFT ENGINEER( TECH LEAD)
THE ROLE:
We are seeking a highly experienced DFT engineer to join our CPU Cores team in Cambridge, UK. The ideal candidate will have a strong technical background and extensive experience in DFT methodologies, particularly in the context of CPU core design and development.
As a DFT engineer in AMD's CPU Cores team, you will have an outstanding opportunity to work on AMD’s next-generation CPU core designs. You will work as part of an experienced, skilled, and motivated engineering team with a track record of success. You will help make AMD’s ambitious future CPU roadmap a reality while working in a highly collaborative environment at the cutting edge of technology.
As a senior member within the DFT team, you will work closely with the Architecture, Design, Verification, Physical Design teams and Product Engineers to achieve first pass silicon success.
THE PERSON:
A successful candidate will exhibit exceptional knowledge in Design for Testability (DFT) and possess extensive experience, complemented by a robust, self-motivated work ethic and strong leadership qualities.
The ideal candidate should demonstrate a genuine passion for modern, complex processor architectures, digital design and verification, and an overall enthusiasm for DFT. As a collaborative team player, you will have outstanding communication skills and experience in working effectively with engineers across various locations and time zones. Your strong analytical and problem-solving abilities will empower you to tackle challenges enthusiastically and with a willingness to learn.
Additionally, you should have a keen eye for detail and the capability to think critically. The role requires a proactive self-starter who can take initiative and independently drive tasks to successful completion.
KEY RESPONSIBLITIES: Strong prior experience in all or at least some of the key areas below would be needed
- Keep abreast with the latest industry trends in DFT domain and help adopt the latest DFT techniques and methodologies in to AMD products.
- Define and implement DFT architecture and features for next generation multi-core microprocessor designs and support their verification effort.
- Work closely with architects, design, verification, physical design and product engineering teams to integrate DFT requirements seamlessly into the overall design process and to develop scalable DFT architectures for complex CPU designs.
- Coordinate with DFT teams across different time zones to develop unified DFT strategies, promoting effective communication and collaboration.
- Work closely with DFT Tool Vendors and drive improvements based on the testability requirements.
- Develop efficient DFx flows and methodology compatible with front end and back end design flows.
- Work with the product, test engineering teams and post-silicon debug teams to ensure successful silicon bring up, to help root-cause any silicon failures and to enhance yield learning & improvement.
- Mentor and coach junior engineers
PREFERRED EXPERIENCE: Strong prior experience in all or at least some of the key areas below would be preferred
- Prior work experience in high-performance and low-power designs would be a huge bonus.
- Understanding of low-power design flows such as power/clock gating, multi-Vt and voltage/frequency scaling etc will be a plus.
- Good understanding of DFT components like JTAG(IEEE 1149.x), IJTAG(IEEE P1687), Core Test(IEEE P1500), SSN(Streaming Scan Network), SSH, Test Compression, OCC etc.
- Excellent Verilog RTL coding, scripting( using Python, Perl, Shell, TCL, Awk, Sed etc) and debugging skills are critical
- Strong experience in Scan based testing and industry standard ATPG CAD tools desired.
- Knowledge of fault models including Stuck-at, Transition, Gate-Exhaustive, Path Delay, IDDQ, Cell Aware etc.
- Knowledge of ATPG pattern verification and gate-level simulation flows using Synopsys VCS and Verdi or other state of the art EDA tools.
- Experience in MBIST implementation and verification will be a strong plus.
- Good understanding of STA concepts having handled DFT timing closure before would be a plus.
- Experience in Spyglass based DFT DRC checks at RTL level would be a plus.
- Experience with Synopsys Design Compiler/Test Compiler/Fusion Compiler etc would be a plus.
- Prior experience in working with Version control systems like perforce, git etc would be critical.
- Understanding of Logic Equivalence, CDC, Lint, UPF/CLP checks would be a plus.
- Familiarity with System Verilog and UVM would be a plus.
- Exposure to post-silicon testing and tester pattern debug are major assets.
- Strong problem solving and debug skills across various levels of design hierarchies.
- Must have good communication skills and the ability to work in a worldwide team environment.
ACADEMIC CREDENTIALS:
- Bachelors or Masters or PhD in Computer engineering/Electrical engineering/Electronics Engineering
#LI-PL1
#LI-Hybrid
#CORE