Staff Verification Design Engineer
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
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STAFF VERIFICATION DESIGN ENGINEER
THE ROLE:
As a Senior Verification Engineer, member of technical staff, you will architect, develop and drive functional coverage models using System Verilog - UVM test benches.
You will actively review and improve verification strategy and architecture of IP testbenches, ensuring test bench scalability, coverage and meeting sign-off targets.
You will actively steer and interact with RTL and Verification team, providing constant feedback and support with balanced mix of hands on approach and leadership.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team driver who has excellent communication skills and experience collaborating with other engineers located in different sites/time-zones.
You have strong analytical and problem-solving skills, architectural and leadership abilities and an eye for design reusage and shifting process to the left, leveraging automated tools and mitigating risks.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified, the scope context and the deliverables dependencies
- Build test plans and realign/enhance verification environment
- Drive team backlog, provide estimations, break down activities, evaluate risks and create mitigation plans
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and SOC engineers to resolve design defects and take corrective actions
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Experience with UVM and SystemVerilog in design and execution verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment, integrating AI tools
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Experience driving a unit verification team is a plus
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
#LI-Hybrid
#Iasi
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
Benefits offered are described: AMD benefits at a glance.
AMD does not accept unsolicited resumes from headhunters, recruitment agencies, or fee-based recruitment services. AMD and its subsidiaries are equal opportunity, inclusive employers and will consider all applicants without regard to age, ancestry, color, marital status, medical condition, mental or physical disability, national origin, race, religion, political and/or third-party affiliation, sex, pregnancy, sexual orientation, gender identity, military or veteran status, or any other characteristic protected by law. We encourage applications from all qualified candidates and will accommodate applicants’ needs under the respective laws throughout all stages of the recruitment and selection process.
STAFF VERIFICATION DESIGN ENGINEER
THE ROLE:
As a Senior Verification Engineer, member of technical staff, you will architect, develop and drive functional coverage models using System Verilog - UVM test benches.
You will actively review and improve verification strategy and architecture of IP testbenches, ensuring test bench scalability, coverage and meeting sign-off targets.
You will actively steer and interact with RTL and Verification team, providing constant feedback and support with balanced mix of hands on approach and leadership.
THE PERSON:
You have a passion for modern, complex processor architecture, digital design, and verification in general. You are a team driver who has excellent communication skills and experience collaborating with other engineers located in different sites/time-zones.
You have strong analytical and problem-solving skills, architectural and leadership abilities and an eye for design reusage and shifting process to the left, leveraging automated tools and mitigating risks.
KEY RESPONSIBILITIES:
- Collaborate with architects, hardware engineers, and firmware engineers to understand the new features to be verified, the scope context and the deliverables dependencies
- Build test plans and realign/enhance verification environment
- Drive team backlog, provide estimations, break down activities, evaluate risks and create mitigation plans
- Build the directed and random verification tests
- Debug test failures to determine the root cause; work with RTL and SOC engineers to resolve design defects and take corrective actions
- Review functional and code coverage metrics – modify or add tests or constrain random tests to meet the coverage requirements
PREFERRED EXPERIENCE:
- Proficient in IP level ASIC verification
- Proficient in using UVM testbenches and working in Linux and Windows environments
- Experienced with Verilog, System Verilog, C, and C++
- Graphics pipeline knowledge
- Experience with UVM and SystemVerilog in design and execution verification frameworks and testbenches, processes and flows
- Automating workflows in a distributed compute environment, integrating AI tools
- Exposure to simulation profile, efficiency improvement, acceleration, HLS tools/process
- Strong background in the C++ language, preferably on Linux
- Good understanding and hands-on experience in the UVM concepts and SystemVerilog language
- Scripting language experience: Perl, Ruby, Makefile, shell preferred.
- Exposure to leadership or mentorship is an asset
- Experience driving a unit verification team is a plus
ACADEMIC CREDENTIALS:
- Bachelors or Masters degree in computer engineering/Electrical Engineering
#LI-PL1
#LI-Hybrid
#Iasi