Summer 2024 Design RTL Engineer Co-Op/Intern
WHAT YOU DO AT AMD CHANGES EVERYTHING
We care deeply about transforming lives with AMD technology to enrich our industry, our communities, and the world. Our mission is to build great products that accelerate next-generation computing experiences – the building blocks for the data center, artificial intelligence, PCs, gaming and embedded. Underpinning our mission is the AMD culture. We push the limits of innovation to solve the world’s most important challenges. We strive for execution excellence while being direct, humble, collaborative, and inclusive of diverse perspectives.
AMD together we advance_
As a Co-op student, you can make an immediate contribution to AMD's next generation of technology innovations. We have a dynamic, high-energy work environment, filled with expert employees, and unique opportunities for developing your career. You will have the opportunity to connect with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. With AMD, you can get hands-on experience that will give you a competitive edge in the workforce.
SUMMER 2024 DESIGN RTL ENGINEER CO-OP/INTERN
LOCATION: Boxborough, MA
On-Site: This role requires the student to work from the Boxborough, MA office throughout the duration of the Co-op/Intern term. First-time Co-ops/Interns should work full-time and onsite.
PROGRAM TERM: Summer: May 20, 2024 – August 9, 2024
WHAT YOU’LL BE DOING:
The Memory IO team is looking for passionate RTL design engineers for the development of high-speed LPDDRx, DDRx, as part of a unique coop experience. Be a part of the definition, design, and development phase of industry-leading Memory IP. This opportunity includes logic development, timing, and floor planning of the memory subsystem as well as close interaction and coordination with the DDR Subsystem verification team. Come be a part of a cutting-edge team that delivers Industry leading IP and help our experts in RTL, Firmware, BIOS and architecture teams develop leading edge Memory interfaces!
Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a Memory team to develop RTL for Memory Subsystem. Are you looking for a ground floor opportunity that requires being a self-starter and the ability to independently drive tasks to completion? We are also looking for strong interpersonal and communication skills – this position will be working collaboratively across the AMD organization! If this sounds like you, please apply!
KEY QUALIFICATIONS:
- Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
- Knowledge and proven implementation of System Verilog and Verilog language with respect to RTL design
- Excellent debug skills and knowledge of debugging RTL designs with industry standard tools
- Development and maintenance of IP integration, documentation, timing, and floor planning
- Develop block level documentation as well as timing diagrams.
- Knowledge of standard IP interfaces, communication of interfaces, and IP interface protocol and utilization
- Clock domain crossing implementation experience
WHAT WOULD SET YOU APART:
- Understanding of Systems & SoC architecture, with expertise in Memory sub-system, Fabrics, CI/O subsystems, Clocks, Resets, and Security
- Experience analyzing System-level Micro-Architectural features to identify performance bottlenecks within different workloads.
- Experience in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
- Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller RTL design and development.
- Knowledge and experience developing SVA/OVL and synthesizable assertions.
- Experience stitching block level IP together to form subsystems.
- VCS and Zebu Emulation verification and debug experience.
- Experience using of git and perforce.
- UPF experience and knowledge of power supply implementations across subsystems and writing logic and timing constraints to handle clock domain crossings
- Experience using Python.
WHO WE’RE LOOKING FOR:
- On-going Bachelor's degree in Electrical or Computer Engineering and relevant experience, or
BENEFITS:
- Compensation Range $32.00-$42.00 hourly commensurate with experience
- Healthcare coverage, dental and vision
- Paid holidays
- Relocation stipend
- Education assistance for required Co-op/Intern course
As a Co-op student, you can make an immediate contribution to AMD's next generation of technology innovations. We have a dynamic, high-energy work environment, filled with expert employees, and unique opportunities for developing your career. You will have the opportunity to connect with AMD leaders, receive one-on-one mentorship, attend amazing networking events, and much more. With AMD, you can get hands-on experience that will give you a competitive edge in the workforce.
SUMMER 2024 DESIGN RTL ENGINEER CO-OP/INTERN
LOCATION: Boxborough, MA
On-Site: This role requires the student to work from the Boxborough, MA office throughout the duration of the Co-op/Intern term. First-time Co-ops/Interns should work full-time and onsite.
PROGRAM TERM: Summer: May 20, 2024 – August 9, 2024
WHAT YOU’LL BE DOING:
The Memory IO team is looking for passionate RTL design engineers for the development of high-speed LPDDRx, DDRx, as part of a unique coop experience. Be a part of the definition, design, and development phase of industry-leading Memory IP. This opportunity includes logic development, timing, and floor planning of the memory subsystem as well as close interaction and coordination with the DDR Subsystem verification team. Come be a part of a cutting-edge team that delivers Industry leading IP and help our experts in RTL, Firmware, BIOS and architecture teams develop leading edge Memory interfaces!
Are you looking to take on and tackle advanced engineering challenges? We are looking for open minded, flexible, innovative, and creative Engineers looking to join a Memory team to develop RTL for Memory Subsystem. Are you looking for a ground floor opportunity that requires being a self-starter and the ability to independently drive tasks to completion? We are also looking for strong interpersonal and communication skills – this position will be working collaboratively across the AMD organization! If this sounds like you, please apply!
KEY QUALIFICATIONS:
- Work cross functionally with IP/Domain architects to identify and assess complex technical issues/risks and develop architectural solutions to achieve product requirements
- Knowledge and proven implementation of System Verilog and Verilog language with respect to RTL design
- Excellent debug skills and knowledge of debugging RTL designs with industry standard tools
- Development and maintenance of IP integration, documentation, timing, and floor planning
- Develop block level documentation as well as timing diagrams.
- Knowledge of standard IP interfaces, communication of interfaces, and IP interface protocol and utilization
- Clock domain crossing implementation experience
WHAT WOULD SET YOU APART:
- Understanding of Systems & SoC architecture, with expertise in Memory sub-system, Fabrics, CI/O subsystems, Clocks, Resets, and Security
- Experience analyzing System-level Micro-Architectural features to identify performance bottlenecks within different workloads.
- Experience in power management microarchitecture, low power design and power optimization, along with power impact at architecture, logic design, and circuit levels
- Experience with DDR/JEDEC standard IP, DDR PHY, or Memory Controller RTL design and development.
- Knowledge and experience developing SVA/OVL and synthesizable assertions.
- Experience stitching block level IP together to form subsystems.
- VCS and Zebu Emulation verification and debug experience.
- Experience using of git and perforce.
- UPF experience and knowledge of power supply implementations across subsystems and writing logic and timing constraints to handle clock domain crossings
- Experience using Python.
WHO WE’RE LOOKING FOR:
- On-going Bachelor's degree in Electrical or Computer Engineering and relevant experience, or
BENEFITS:
- Compensation Range $32.00-$42.00 hourly commensurate with experience
- Healthcare coverage, dental and vision
- Paid holidays
- Relocation stipend
- Education assistance for required Co-op/Intern course