Systems IP - Senior Design Engineer
This position is an excellent opportunity for a hard-working RTL design engineer looking for a fast-paced role employing the latest hardware design and verification methodologies to develop complex and highly configurable hardware IP that sit at the heart of Arm-based Systems!
Working as the System IP team and engaging with the world’s most famous technology companies, we are driving innovation into all areas that compute is possible to help us build better solutions for the billions of people using our technology worldwide. The team leads the creation of a range of popular Arm IP, like Interconnects/NoCs, MMUs and ISPs used in multiple innovative products targeting high-end mobile, networking, and enterprise markets!
Our Interconnect team develops the Arm Corelink Interconnect IP. This highly scalable IP is designed for intelligently connected AMBA-compliant SoC connectivity and can be customised for multiple performance points.
A Senior Design Engineer will work independently on the development of one or more functional blocks of the IP. They are required to have an understanding across all the elements that enable a products’ successful delivery. This includes low-power design techniques and the awareness of the impact of design decisions on system performance. In addition, they will also have the ability to produce designs that are area efficient, and the verification techniques that are employed to ensure high-quality innovative designs.
- Logic implementation as well as front-end implementation tasks like synthesis, logic equivalence check, and STA
- The planning, tracking and coordinating of individual tasks to meet high quality goals at the planned time
- Working closely with the verification team to share the responsibility of delivering high quality hardware designs, including debugging functional or performance issues with the RTL using simulation and debug tools
- Improving design methodology across the System IP group and wider Arm design community
- Providing direction and mentoring to other junior members of your team as they learn new things.
Required Skills and Experience:
- Demonstration of a strong delivery record of high quality, low power, high performance complex micro-architecture and RTL implementations in reasonable timescales.
- Be able to navigate and make high-level design trade-offs and articulate the rationale for those choices.
- Knowledgeable on ASIC/FPGA design methodology, IP signoff methods with a deep understanding on timing/area/complexity trade-offs for complex data path designs
'Nice to Have' Skills and Experience:
- CPU or compute subsystem memory micro-architecture
- Multiprocessing microarchitecture experience including knowledge of cache coherence and bus protocols (e.g. AMBA5 CHI, AMBA4 ACE or AXI)
- Experience with any of System Verilog, UVM and formal verification
- Knowledge of a scripting language such as Perl, Tcl, C shell