High Level Synthesis Design Engineer

Celestial AI

Posted Sept. 17, 2023

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<div class="content-intro"><p><em>Celestial AI is the creator of the Photonic Fabric optical interconnect technology platform. Photonic Fabric provides the foundational technology for optically scalable, disaggregated data centers, to unleash advancements in AI with sustainable and profitable business models.&nbsp; Celestial AI has assembled a highly experienced team of industry leaders who have a track record of building multiple successful technology businesses.&nbsp; The company recently closed a Series B financing to accelerate our growth, bringing total funding to over $160 million. Celestial AI serves an addressable market that is projected by Cowen &amp; Company to exceed $200 billion in 2030.</em></p></div><p><strong>Job Description:</strong></p> <p>&nbsp;</p> <p>As an HLS design engineer, you will contribute to the core processor functionality that helps enable Celestials unique value proposition. You will collaborate with architects and a small team of design engineers to implement the specified algorithms and control structures using HLS, while simultaneously making performance, power, area and latency optimizations. Using the fast iteration times enabled by HLS you will often evaluate a range of possible implementations before choosing the best suited version.</p> <p>&nbsp;</p> <p><strong>ESSENTIAL DUTIES AND RESPONSIBILITIES:</strong></p> <ul> <li>Implement functionality as specified in the Celestial architecture simulator in HLS (System C/C++). Negotiate changes with architects as needed to meet performance goals.</li> <li>Author detailed design documents.</li> <li>Perform power, area, and performance trade-off analysis.</li> <li>Collaborate with the DV team and review test plans to ensure bug free designs.</li> <li>Drive coverage closure of your designs.</li> </ul> <p>&nbsp;</p> <p><strong>QUALIFICATIONS:</strong></p> <ul> <li>5+ years of RTL design experience (Verilog, SystemVerilog, digital microarchitecture).</li> <li>Extensive experience coding C/C++.</li> <li>Experience with High Level Synthesis for ASICs or FPGAs.</li> <li>Knowledge of basic processor architecture.</li> <li>Experience with full ASIC design cycle (spec through bring-up) preferred.</li> <li>BS plus 7 years relevant experience. MS preferred.</li> </ul> <p>&nbsp;</p> <p><strong>Location:&nbsp; </strong>San Francisco Bay Area or Orange County, CA</p> <p>&nbsp;</p> <p style="line-height: 1;">For California location:</p> <p class="xxmsonormal"><span style="font-size: 10.5pt; color: black;">As an early startup experiencing explosive growth, we offer an extremely attractive total compensation package, inclusive of competitive base salary and a generous grant of our valuable early-stage equity. &nbsp;The target base salary for this role is approximately</span> $155,000.00 - $175,000.00. The ba<span style="font-size: 10.5pt; color: black;">se salary offered may be slightly higher or lower than the target base salary, based on the final scope as determined by the depth of the experience and skills demonstrated by candidate in the interviews.</span></p> <p>&nbsp;</p><div class="content-conclusion"><p>We offer great benefits (health, vision, dental and life insurance), collaborative and continuous learning work environment, where you will get a chance to work with smart and dedicated people engaged in developing the next generation architecture for high performance computing.</p> <p>Celestial AI Inc. is proud to be an equal opportunity workplace and is an affirmative action employer.</p> <p>&nbsp;</p> <p>#LI-Onsite</p></div>