Semiconductor Design (ASIC/FPGA) Trainee / Internship
<h3 style="padding: 0px;margin-top:0px;margin-bottom: 4px;">Launch innovations in nearly every commercial and defense aircraft platform</h3><p>We have an opportunity for an Engineering Support Intern to join us at Honeywell, in Prague, where you will be responsible for working on digital design using System Verilog, support activities as integration and testing. This is a hybrid role, 3 + 2 days model.</p><p>Since the invention of autopilot in 1914, we’ve been a leader in innovation for the Air Travel industry. Today, thousands of Honeywell products are used in aircraft and airports around the world. Everyday 140,000 Honeywell air turbine starters bring to life commercial and military aircraft, industrial and marine equipment.</p> <p><b><i>More sustainable travel, safer and more efficient flying and a focus on cutting-edge innovation. </i></b></p><p style="margin-bottom: 0; text-align: justify; line-height: normal"><b><span style="font-family: "Segoe UI""><font size="2"><span style="text-decoration: underline">Key responsibilities</span></font></span></b></p><ul type="disc" style="margin-top: 0"> <li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">Digital design (System Verilog / VHDL coding), verification, simulation, synthesis, and static timing analysis</font></span></li> <li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">Integration and Test Support</font></span></li> <li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">Provide Customer Support</font></span></li> <li style="margin-bottom: 0; line-height: normal"><span style="font-family: Calibri"><font size="2">Prepare Documentation</font></span></li></ul><p> </p><p style="margin: 0 0 0 0.25in; line-height: normal"><i><span style="font-family: Calibri"><font size="2">Please note that due to export restrictions, we will only be able to take into consideration applicants with an EU, UK or US citizenship.</font></span></i></p><p style="margin-bottom: 0"><font size="2"><strong><span style="text-decoration: underline">Key skills and qualifications</span></strong></font></p> <ul type="disc" style="margin-top: 0"><strong><span style="text-decoration: underline"> </span></strong><li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">University level experience in ASIC/FPGA development</font></span></li> <li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">Knowledge or practical experience of VHDL, Verilog or System-Verilog</font></span></li> <li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">Basic knowledge of the ASIC/FPGA design tools: simulators, STA tools, synthesis, etc.</font></span></li><li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">Intermediate level of English language </font></span></li><li style="margin-bottom: 0; line-height: normal"><span style="font-family: "Segoe UI""><font size="2">EU or US citizenship</font></span></li> </ul><div><p style="line-height: normal"><span style="color: #000000; font-family: Calibri">We are an equal opportunity employer and value diversity at our company. We do not discriminate based on race, religion, color, national origin, gender, sexual orientation, age, marital status, veteran status, or disability status.</span></p> <p style="line-height: normal"><span style="color: #000000; font-family: Calibri">We will ensure that individuals with disabilities are provided reasonable accommodation to participate in the job application or interview process, to perform crucial job functions, and to receive other benefits and privileges of employment. Please contact us to request accommodation.</span></p><p style="text-indent: -0.25in"><span style="font-family: Symbol"><span>·<span style="font: normal normal normal normal 7pt / normal "Segoe UI""> </span></span></span><b>Innovate to solve the world's most important challenges, join us now!</b></p>#FutureShaper</div><div></div><div>EMEAUR</div><h3 style="padding: 0px;margin-top: 10px;margin-bottom: 4px;">Additional Information</h3><ul><li style="margin-bottom: 1px;"><b>JOB ID: </b>req416521</li><li style="margin-bottom: 1px;"><b>Category: </b>Engineering</li><li style="margin-bottom: 1px;"><b>Location: </b>V Parku 2326/18, budova 10,2.&3.p.,Prague,PRAHA,14800,Czech Republic</li><li style="margin-bottom: 1px;">Nonexempt</li><li style="margin-bottom: 1px;"></li></ul><div class="embed-responsive embed-responsive-16by9"><iframe src="https://www.youtube.com/embed/AVdv-Uy07rQ">Early Career (ALL)</iframe></div>