Analog & Mixed-Signal Verification Engineer (f/m/div)
Do you have experience in Analog & Mixed-Signal Verification or want to grow in this field? Do you want to be part of a team who shapes the future of mobility with products and solutions that make cars clean, safe and smart? Then, we have the right challenge for you at our R&D Center in Padova! We are dedicated to pushing the boundaries of technology to enhance the efficiency and performance of automotive systems. We are currently seeking a highly motivated Analog & Mixed-Signal Verification Engineer to join our dynamic team and contribute to cutting-edge projects in the automotive industry.
As an Analog & Mixed-Signal Verification Engineer, you will be responsible for the overall analog/mixed-signal (AMS) verification, contributing to the success of the project team for the development of Integrated Circuits for Automotive applications. Your work will involve collaborating closely with other teams to develop high-performance solutions.
In your new role you will:
- Perform top-level verification of analog / mixed-signal devices;
- Plan, implement, and maintain the requirements tracing flow, documents and database;
- Be responsible for the blocks/modules’ signoff.
- Be responsible for the system partitioning and simulation strategy (transistor level, behavioral level, digital gates);
- Work closely with design and concept engineering teams in order to achieve very high-quality deliveries;
- Constantly align with digital and post-silicon counterparts to achieve the highest synergies in targets, implementation, and methods;
- Contribute to the feasibility study, specification, and testing concept;
- Create reports and technical documentation;
- Plan & track tasks, including effort estimation.
You are best equipped for this task if you have:
- A Master’s degree in Electronic/Automation Engineering, Mathematics, Physics, or equivalent field of studies;
- 1 to 3 years of industry experience in analog & mixed-signal verification or equivalent verification field;
- Specific knowledge of microelectronic devices, common architectures, and related analog/mixed-signal circuit design;
- Basic knowledge of hardware description language (Spice), with VHDL, Verilog, and System Verilog being a plus;
- Experience with common simulation tools (by Cadence, Mentor, and Synopsys);
- Good knowledge of Unix OS and scripting languages (Perl, Python);
- Knowledge of UVM methodology is a plus;
- Proactivity and focus on results, while keeping a team player mentality;
- Fluency in English. Knowledge of Italian is valued and German is a plus.