Lead Principal Engineer Design for Test
The successful candidate will be part of a chip/SoC integration design team working in the Infineon IoT, Compute, and Wireless organization(ICW). As part of the team, you will develop the next generation of industry-leading, low-power, best-in-class silicon products for the IoT,consumer, and industrial markets. These products are focused on optimizing static and dynamic power of the system, integrating high degrees of analog and memory, and maximizing performance of the process node and options. This role is responsible for driving DFX efforts for the ICW organization. In this role, you will define and drive implementation of state-of-the-art DFX solutions for some of the most advanced ultra-low power IoT and Microcontroller semiconductor devices. In this highly visible role, you will work with System Architects, Chip Architects/Leads, DFX Design Teams, IP Designers, Physical Designers,Test Engineers, Product Engineers, and Verification Engineers to creatively develop scalable and reusable DFX solutions
In your new role you will:
- Driving a cross-functional team of System Architects, ChipArchitects/Leads, Test Engineers, and other DFX experts to define and document platform-level, chip-level, and IP-level DFX architectures(macro-architecture and micro-architecture) for a variety of IoT and connectivity enabled Microcontrollers
- Contributing to the definition and implementation of DFX IPs
- Driving the definition and methodology for DFT integration and test ability of reusable IPs
- Contributing to the definition, development, and implementation flow power aware and cost-effective DFX architectures for all levels of design hierarchy, to ensure that products meet testability and coverage requirements, while having optimal ATPG test times
- Providing guidance and support for Chip Architects/Leads, DF Tengineers, IP Designers, Verification Engineers, and Physical DesignEngineers at various stages of Project Execution
- Providing silicon debug support to enable timely silicon bring-up, problem analysis, design feedback, and yield optimization
- Continuously providing effective innovation in DFX architectures andmethodologies
- Contribute to multi-die DFX solutions
- Participate in cross-functional design/architecture reviews
- Participate in cross-functional test plan verification reviews
- Review DFX verification plans for all levels of design hierarchies
- Contribute to the development easy to reuse DFX pattern generationmethodologies
- Contribute to DFX pattern development
- Contribute to DFX verification effort
- Support Physical Design implementation to ensure final designimplementation meets DFT requirements
- BS/MS degree in Electrical/Computer Engineering; minimum of 8 years of DFX/DFT design and architecture experience.
- Experience with high volume manufacturing requirements and Test development
- Expertise in Siemens‘ Tessent tooling
- Familiarity with low power MCUs and low power test ability
- Deep understanding of scan test, memory BIST, IO test, AMS test, and low power test methodologies and technologies
- Clear understanding of Test Vector development, formats, and languages
- Solid understanding of the impact of clock trees and physicalimplementation on DFT testing
- Strong knowledge of RTL design involving Verilog and System Verilog
- Good awareness of design verification flows and methods
–Connected Secure Systems (CSS) is at the heart of the IoT –
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