Master Thesis: Application of generative AI technology for SystemVerilog code generation (f/m/div)
You love technology, a dynamic environment and want to be part of state-of-the-art developments? At Infineon's Design Center Villach (DCV) we connect the real with the digital world. We foster innovation and develop circuits that process digital and analog signals. Do you have an affinity for programming and AI and are close to finishing your studies in Computer Science, Electrical Engineering, or a related field? We are seeking a highly motivated and talented student to join our team for a master’s thesis project that focuses on generative AI for code generation in IC product development. As a key contributor to this project, you will have the opportunity to explore the potential of cutting-edge AI technology in the semiconductor industry, while also gaining valuable insights into the processes of IC product development. This could be YOUR chance! Join our team in Villach in the area of Functional Verification Engineering and boost your career.
In your new role you will:
- Develop a generative AI model that can efficiently generate SystemVerilog code for IC product development
- Contribute to optimizing our design and verification processes
- Work closely with our cross-functional team of experts to design, train, and evaluate the performance of the AI model
- Deploy and integrate the AI model into our existing development workflows, optimizing our design and verification processes
The completion of a Master's thesis within the employment is possible and supported.
This thesis has to be written in cooperation with an university.
Further Information
Type of employment: Temporary / Full-time or Part-time (flexible working hours from Monday to Friday between 6 a.m. and 7 p.m.)
Duration: min. 12 months
You successfully meet the requirements, if you are a Master student from the field of Computer Science, Electrical Engineering or similar. You are best equipped for this task if you additionally offer:
- A solid understanding of programming concepts and familiarity with Python programming language
- A basic understanding of IC digital design and verification and experience with SystemVerilog and UVM as a plus
- Previous experience with AI, machine learning, AI agent frameworks (e.g. Langchain, CrewAI) and/or version control systems like GIT is a significant advantage
- A self-motivated and curious working style with good communication skills and the ability to work independently
Please attach the following documents (German or English) to your application:
- Motivation letter
- CV
- Certificate of matriculation at a university
- Latest Transcript of records (not older than 6 months)
- Highest completed educational certificate (Bachelor certificate for Master students)
- Reference letter (optional)