Are you a Master's Student looking to write your thesis in a fast-paced and innovative company? Do you want to start your career within a highly specialized team of engineers? Then this opportunity was made for you! Join our vibrant and ever-evolving R&D Center in Padova where stimulating opportunities are waiting for you!
Thesis topic: "Generative AI in functional verification"

Generative AI in functional verification is an emerging field to automate the verification of complex digital circuits. The objective of generative AI is to assist designers and verification engineers in finding and fixing complex bugs faster and more efficiently. With the increasing complexity of integrated circuits, traditional methods of verification have become time-consuming and error-prone. Therefore, generative AI has the potential to revolutionize the field by providing a faster, more reliable, and more thorough verification process.

During this experience, you will be able to:

• Get familiar with industry-standard Metric-driven digital verification techniques based on System Verilog and UVM methodology
• Automate verification implementation with a Large Language Model (LLM): investigate an LLM-based flow for automated generation of System Verilog assertions and other verification components, as well as documentation
• Team up with expert engineers
• Be part of a diverse and international company
• Receive guidance and feedback from your supervisor

You are a team player with good communication skills. Furthermore, you are a fast learner and have a proactive personality with attention to detail at all times.

You are best equipped for this task if you:

• Are a Master’s degree student in the field of Electronics, Computer Science, Physics or similar areas
• Know electronics basics
• Know programming-scripting languages (e.g. Python, Unix OS) – is a plus
• Are proficient in English (mandatory)

Please send us your CV in English so we can get to know you better.