Principal Engineer Functional Verification & Methodology (f/m/div)*
UVM and formal verification are not just abstract terms for you, but your daily tools of the trade? Would you like to further develop your in-depth technical knowledge in the field of digital verification and share it with your colleagues? As a Principal Engineer Functional Verification & Methodology, you will improve existing methods in terms of quality and efficiency and develop new methods for the next generation of our products. You will also take on the technical management of a small verification team for various microcontroller-based ICs in our wide range of products. With this position, you will enter our "Technical Ladder" career path. The Technical Ladder is a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value.
In your new role you will:
- Define and implement verification concepts for complex SoCs using leading edge methodologies such as metric-driven, formal, power-aware as well as HW/SW co-verification
- Architect state-of-the-art test benches for IPs, sub-systems and SoCs.
Coordinate the overall verification strategy, including SoC verification and validation - Define and steer verification management activities such as verification planning, verification tracking and reporting as well as requirement-based verification
- Conduct the clarification of verification requirements in cross-functional collaboration with concept, digital and analog/mixed-signal design, software and physical implementation teams across multiple sites
- Lead the verification of IC projects comprehensively on module and system level and ensure a work process compliant and high-quality verification sign off
- Proactively drive the improvement of existing verification methodologies and flows
- Mentor Junior Engineers along with technical leadership of the project
Beyond, you are best equipped for those tasks if you have:
- A degree in Electrical/Electronic Engineering, Computer Science or equivalent
- More than 6 years of experience within the semiconductor industry, including roles of technical leadership
- Strong know-how of state-of-the-art verification methodologies like coverage-driven verification, formal verification, power-aware verification as well as HW/SW co-verification and mixed-signal verification concepts
- Proficiency in System Verilog, VHDL, Verilog, UVM and scripting languages
- Experience with a SoC verification test bench architectures
- Expertise in using leading simulators, linters, test bench qualification tools as well as data and verification management systems
- Knowledge in functional safety and security is a plus and preferably interest in technical team management
- Strong communication skills in English, German is a plus not mandatory