Principal Engineer Prototyping (f/m/div)
You are searching for a new challenge and are open for an international adventure? You like to drive innovation through your technical and personal contribution? This is your chance! Join us as Principal Engineer Prototyping (f/m/div) and enrich our team with your open-minded personality and technical skills.
In your new role you will:
- Be responsible to develop FPGA, Embedded System, Application Based SoC Prototype Platforms (Hardware, Emulation, Mixed-signal)
- Work on prototype design and the implementation from a System and Product level perspective
- Automation and scripting based on various EDA tooling and in-house tooling
- Concept and Architecture verification as well as result driven analysis and bug finding
- Cover the System Behavioral modeling, Digital Design, Test bench development
- Deep-dive into SoC and IP level design and architecture
- At least 10 years’ experience with projects related to Full System FPGA Prototyping, Verification and Validation
- Familiar with one or more EDA Emulation and FPGA Prototyping tools, like Xilinx, Synopsys, Altera, Siemens, etc.
- Ability to work with multiple design languages (like System Verilog, Verilog, Python, Verilog A, C++, System C)
- Willingness to take up technical challenge and communicate on a multi-team, multi-site collaboration manner
- A broad understanding of different ASIC product portfolios
- Strong interest in innovation and exploration
We offer competitive salaries and additional benefits based on your performance, experience and qualification. The employment is in accordance with the collective salary and wage agreement for employees of the electrical and electronics industry, employment group I (https://www.feei.at/wp-content/uploads/2022/05/minimum-salaries-white-collar-workers-2023.pdf). The monthly salary is paid 14 times p.a. We offer a higher compensation depending on your expertise and skills.