Principal Verification Engineer for UWB (f/m/div)
Ultra-wideband (UWB) is emerging as preferred chip technology for secure, centimeter accurate and reliable distance measurement for numerous applications across including car access, door access in residential and hospitality, tap-free mobile payments and real-time localization systems (RTLS), among many others. In addition, new UWB standards are being developed such as IEEE 802.15.4ab bringing UWB technology into new domains for child safety and lossless audio streaming. UVM and Formal Verification are not just abstract terms for you, but your daily tools of the trade? You have technical expertise in the area of UWB and you are eager to share this with your colleagues? As Principal Verification Engineer for UWB, you will be responsible together with a strong team for ensuring that our UWB IP meets the specified requirements in all modes and configurations. With this position, you will enter our "Technical Ladder" career path. The Technical Ladder is a special career path for those who share innovative ideas, demonstrate comprehensive technical knowledge, show thought leadership, possess problem solving abilities and are able to create business value.
In your new role you will:
- Define and implement verification concepts for UWB IP using leading edge methodologies such as constrained random, formal as well as power aware
- Architect UVM-based environments for our UWB module and its subcomponents
- Define and steer verification management activities such as verification planning, verification tracking and reporting as well as requirement-based verification
- Lead the verification of complex digital IPs comprehensively and ensure a smooth work process and high-quality verification signoff
- Proactively drive the improvement of existing verification methodologies and flows
- Contribute to the team’s growth by mentoring and coaching young engineers
You are best equipped for this task if you have:
- A degree in Electrical Engineering, Computer Science, or comparable
- At least 6 years professional experience in the field of functional verification
- Knowledge of verification methodologies (UVM, eRM, ABV, formal), various verification EDA tools and complex module test benches
- Knowledge about UWB protocol is a plus
- Rich expertise in HVLs, such as SystemVerilog (preferred) or Specman e
- Good knowledge of OOP
- Knowledge in script languages (Perl, Python, etc.) and data management systems (GIT, Clearcase, Perforce, etc.)
- Fluent English communication skill