Senior Staff Digital Design Engineer (f/m/div)
Infineon is a leader in automotive semiconductor innovation. We are building a new team in Cork to work on our Automotive Programmable System on a Chip (PSoC) products for applications in battery management, smart sensing, and human machine interfaces (HMI). We are looking for applications from candidates with analog design, digital design, digital verification, mixed signal verification, chip level integration, project management and ISO safety requirements experience. In this group you will be part of a small, agile team working together on taking customer requirements and implementing them into the next generation of Infineon automotive products. This team will work closely with and complement our existing experienced PSoC teams in the US, Japan and India. We are seeking ambitious, talented engineers who want to join our dynamic and experienced PSoC group and take their technical knowledge to the next level and be part of the next wave of PSoC development in Infineon.
On this new role, you will have complete control over your career growth, as we believe in providing limitless opportunities for our employees. You will be part of a highly dynamic and interactive team environment, where you will be able to collaborate with like-minded individuals and work towards achieving common goals.
In addition to the above, your responsibilities will include:
- Support the IP design for our next generation digital and mixed signal microcontroller products (Infineon is leading the industry in developing Automotive chips);
- Design RTL, using associated digital flows, including synthesis, and DFT analysis;
- Collaborate with our high-performance analog design team and chip integration team to bring exciting products to market.
- A University Degree in Electrical Engineering or similar field (Masters Degree would be preferred);
- At least 5 years of professional experience;
- Track record of designing digital IP from concept to production;
- Strong digital logic design skills with background writing well-structured RTL (Verilog/ SystemVerilog);
- Practical simulation, debugging, synthesis and timing closure experience;
- Proficiency at developing timing constraints;
- Acquaintance with DFT analysis and coverage closure;
- Familiarity with multi-voltage designs and creating UPF files;
- Knowledge of clock domain crossing and power saving techniques;
- Experience utilizing DRC tools such as: Lint, CDC, and LEC;
- Functional Safety design experience is an advantage (FuSa defined by ISO 26262;
- Strong English written and verbal communication skills.