Senior / Staff Engineer - Digital Verification

Infineon Technologies

Verilog SystemVerilog

Posted Sept. 16, 2024

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We're seeking a Digital Verification Engineer who will champion the verification of digital designs, grasp requirements and specifications, and lead the development of test plans and test benches.
In your new role you will:

• Be responsible for the verification of digital designs;
• Be able to understand requirements & specifications;
• Focus on Test plan and test bench development;
• Be responsible for IP verification (Formal, SystemVerilog, UVM);
• Support the Flow & Methodology improvements;

• Degree in Electronic or Computer Engineering;
• Min 3 years of industry experience in digital verification;
• Development of verification environments and methodologies at block subsystem level;
• Extensive knowledge of SystemVerilog / Verilog / UVM / VMM;
• Fluency in English.